| --- Log opened Tue Apr 01 00:00:45 2014 | ||
| stekern | ah, nothing compares to a nice .vcd with the morning coffee | 02:44 |
|---|---|---|
| stekern | hard to say anything definite with so little signals captured, but if decode is stuck at c0003d94, c0003d8c (l.mtspr r0,r4,0x1802) is then in ctrl/mem | 02:50 |
| stekern | where does that l.mtspr go? | 02:51 |
| stekern | because, my guess is either that the mtspr get stuck or the branch to c0003d8c | 02:52 |
| stekern | because that is already being fetched | 02:53 |
| stekern | ...but since c0003d8c is already in icache, that doesn't seem likely | 03:00 |
| stekern | so, I'd go for logs of the mtspr signals | 03:02 |
| stekern | throw in the padv_ signals too | 03:02 |
| stekern | they are the !stall signals | 03:03 |
| stekern | olofk: actually, there was this one thing I still had pending for fusesoc, it's hidden in the ISE pull request: https://github.com/skristiansson/fusesoc/commit/57dbf604e57722b563bacd4672b6bd2b9dcc87b6 | 03:31 |
| stekern | I think the --64bit argument should be passed by Quartus as well, since it'd be a lot nicer to have that as an external argument. | 03:32 |
| stekern | right now I'm passing that with the QUARTUS_OPTIONS thing in the .core, but I feel that argument doesn't belong 'hardcoded' there | 03:33 |
| stekern | ...and now I remembered another thing... *throws olofk a lifebuoy* | 03:46 |
| olofk_ | stekern: I saw that in your original ISE request and like it much better than the current approach | 05:30 |
| olofk_ | I'll pull that in separately tonight when I can reach my computer | 05:33 |
| olofk_ | I just noticed your ISE detection also. My plan was to just let the user source settings32/64, but I guess this has the added benefit that it won't pollute the environment after the build | 05:35 |
| stekern | it can probably be made a bit more bullet proof by checking that the detected directroy actually exist | 05:41 |
| stekern | and throw an error with a message asking the user to set --ise_path | 05:41 |
| stekern | if it doesn't | 05:42 |
| olofk_ | I think we should check for the XILINX env to begin with in case the user has already sourced the correct settings file | 05:50 |
| stekern | yeah, that might be a good idea | 05:53 |
| olofk_ | Found todays first good news story :) http://boldport.blogspot.se/2014/04/apple-acquires-boldport.html | 05:54 |
| stekern | todays date doesn't make me at all suspicous ;) | 06:01 |
| stekern | but to be frank, apple have already went down the road with oddly shaped PCBs, that are visible to the user | 06:02 |
| stekern | http://en.wikipedia.org/wiki/IMac_G3 | 06:02 |
| olofk_ | oh god. I have tried so hard to forget all the clear plastic items of the late 90's | 06:09 |
| olofk_ | Everyone seemed to think it was a good idea to show off their PCBs at that time | 06:10 |
| stekern | yeah, I never appreciated that | 06:20 |
| stekern | and I remember that I never liked the G3 design, it looked like a vacuum cleaner | 06:21 |
| olofk_ | stekern _franck__ I'm considering a fusesoc 1.1 (or 1.2 perhaps) release when the ISE support and VHDL bits are in place. Anything else that should go in that release? | 06:26 |
| stekern | qsys support? ;) | 06:31 |
| olofk_ | Ok, but only because it's you ;) | 06:32 |
| _franck_web_ | stekern: thanks, I'll do that when I come back home | 06:57 |
| _franck_web_ | I wrote such a long answer to that guy on the opencores forum about his de1 and it just got lost :( | 07:33 |
| olofk_ | _franck_web_: That sucks :( I always copy the text before I press the submit button. It's a really crap forum on OpenCores | 08:39 |
| _franck_web_ | I also use the "copy before push the button technique" :) but not this time | 08:43 |
| _franck__ | stekern: sometimes it hangs, sometimes not | 12:14 |
| _franck__ | here is a waveform I just captured: http://picpaste.com/pics/503cba7fe95b2923b120f3371f3fb108.1396354416.png | 12:14 |
| stekern | hmmm, why doesn't the ctrl_mtpr_ack_o go high there? | 12:20 |
| _franck__ | I'll capture spr_group_present | 12:23 |
| _franck__ | but yes, it is strange | 12:23 |
| stekern | I bet it has to do with this: https://github.com/openrisc/mor1kx/blob/master/rtl/verilog/mor1kx_lsu_cappuccino.v#L618 | 12:25 |
| stekern | because, isn't it to the dtlb sprs it tries to write? | 12:28 |
| stekern | there's a similar hack in the fetcher for the itlbs | 12:28 |
| _franck__ | AFAIR it is dtlb | 12:29 |
| stekern | looking closer, the condition seems to be fulfilled by the '| spr_bus_we_i' though | 12:30 |
| _franck__ | it access data cache spr | 12:31 |
| _franck__ | DC Block Flush register | 12:32 |
| stekern | oh... | 12:32 |
| _franck__ | I need to watch spr signals at mor1kx_dcache | 12:33 |
| stekern | yes, that might be more fragile... | 12:34 |
| _franck__ | ok, see you in 20 minutes ;) | 12:35 |
| stekern | there was this: https://github.com/openrisc/mor1kx/commit/c2655823f48e40495906a670e20cb89e5a7813f3 | 12:35 |
| stekern | that should improve it, but there migh be issues with it still | 12:36 |
| _franck__ | I'll tell you more tonight | 12:40 |
| olofk_ | That patch could have benefited from some whit space cleanup | 12:40 |
| olofk_ | ah.. or is it a different logic depth | 12:41 |
| stekern | yes, but I didn't like that it was munged together with that patch | 13:01 |
| stekern | but made an exception and merged it anyway | 13:01 |
| stekern | I did that as: case()...endcase; if (rst) set_some_signal; | 13:05 |
| stekern | instead of: if (rst) set_some_signal else case()...endcase | 13:06 |
| stekern | I usually prefer: a=1; if (cond) a=0; | 13:07 |
| stekern | over: if (cond=0) a=0 else a=1; | 13:08 |
| olofk_ | me too | 13:16 |
| rah | http://www.flippybitandtheattackofthehexadecimalsfrombase16.com/ | 14:25 |
| olofk | rah: That was surprisingly fun. I have to show that to my daughter when she's slightly older | 17:42 |
| analognoise | Hey OpenRisc! | 17:46 |
| -!- olofk is now known as OpenRisc | 17:50 | |
| OpenRisc | Hey analognoise | 17:50 |
| -!- OpenRisc is now known as olofk | 17:50 | |
| olofk | _franck__: I hadn't seen this one before http://openocd.sourceforge.net/2014/01/openocd-and-gdb-for-openrisc-orconf-2013 You're famous :) | 18:19 |
| _franck__ | olofk: yeah I saw that one by accident while I was searching thing about openocd :) | 19:32 |
| olofk | _franck__: Same here :) | 19:37 |
| olofk | I only find videos of myself when I search for "dirty sluts" :( | 19:38 |
| _franck__ | lol | 19:39 |
| _franck__ | I pushed the patch for vhdl section | 19:40 |
| olofk | _franck__: No need for "if self.src_files:" | 19:45 |
| olofk | Otherwise everything looks good. I'll remove that line and push it, ok? | 19:46 |
| _franck__ | because it is mandatory ? Just copied it... | 19:46 |
| _franck__ | okay thanks, I'm working on something else right now | 19:46 |
| olofk | Hmm.. it seems like I can't pull orpsoc-cores anymore | 19:54 |
| olofk | Did stekern remove my access rights? :) | 19:54 |
| olofk | hmm... git pull -v shows me that it's stuck at "remote: Compressing objects: 4% (1/21)" | 20:00 |
| olofk | Damn... I managed to get 71% before it got stuck, but now I'm down at 9% | 20:16 |
| rah | olofk: glad you liked it :-) | 20:36 |
| olofk | Removed some local changes and now I can pull it. | 20:45 |
| olofk | spartan6 lx9 is not a big FPGA | 21:03 |
| _franck__ | olofk: do you remember I had problem with https access access from fusesoc at work ? | 21:07 |
| olofk | yep | 21:08 |
| _franck__ | I think it is the solution: http://code.activestate.com/recipes/213238/ | 21:08 |
| _franck__ | I do have a proxy | 21:08 |
| _franck__ | and it does https over http I think (from what I've read) | 21:08 |
| olofk | Networks can be way too complicated | 21:10 |
| _franck__ | I agree. "Are you sure this a proxy which is accessed by https, or rather a proxy that | 21:10 |
| _franck__ | supports CONNECT" | 21:10 |
| _franck__ | I have the second one | 21:10 |
| _franck__ | I have to fix this if I want to hack from my dayjob ! | 21:11 |
| olofk | So that code would have to be in fusesoc to support your kind of connection | 21:12 |
| _franck__ | I think so I didn't do any tests yet | 21:13 |
| olofk | That's like 50% of the whole fusesoc code base :) | 21:13 |
| _franck__ | :) | 21:13 |
| olofk | Yeah, I'm ok with bringing it in if it solves problems, but I know next to nothing about proxies, so you and other people with proxies will have to do the testing | 21:14 |
| olofk | Time to sleep now. VHDL support pushed if you didn't see that, btw | 21:14 |
| _franck__ | I don't know much either | 21:14 |
| _franck__ | ok, gn | 21:14 |
| _franck__ | verilog question. I would like to have a parameter of a instantiated module inside a generate loop to be dependent of my genvar. | 22:09 |
| _franck__ | look: http://pastie.org/private/kubbnwihw7iymsk0lp4rg | 22:10 |
| _franck__ | it does work | 22:10 |
| _franck__ | however, as soon as I try to make it look better, I get The expression for a parameter actual associated with the parameter name ('BUF_WIDTH') for the module instance ('wb_port') must be constant. | 22:10 |
| analognoise | _franck__: If your work has a proxy (but you have internet access) you can get the proxy items from internet explorer | 23:05 |
| --- Log closed Wed Apr 02 00:00:47 2014 | ||
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