IRC logs for #openrisc Tuesday, 2014-04-01

--- Log opened Tue Apr 01 00:00:45 2014
stekernah, nothing compares to a nice .vcd with the morning coffee02:44
stekernhard to say anything definite with so little signals captured, but if decode is stuck at c0003d94, c0003d8c (l.mtspr r0,r4,0x1802) is then in ctrl/mem02:50
stekernwhere does that l.mtspr go?02:51
stekernbecause,  my guess is either that the mtspr get stuck or the branch to c0003d8c02:52
stekernbecause that is already being fetched02:53
stekern...but since c0003d8c is already in icache, that doesn't seem likely03:00
stekernso, I'd go for logs of the mtspr signals03:02
stekernthrow in the padv_ signals too03:02
stekernthey are the !stall signals03:03
stekernolofk: actually, there was this one thing I still had pending for fusesoc, it's hidden in the ISE pull request:
stekernI think the --64bit argument should be passed by Quartus as well, since it'd be a lot nicer to have that as an external argument.03:32
stekernright now I'm passing that with the QUARTUS_OPTIONS thing in the .core, but I feel that argument doesn't belong 'hardcoded' there03:33
stekern...and now I remembered another thing... *throws olofk a lifebuoy*03:46
olofk_stekern: I saw that in your original ISE request and like it much better than the current approach05:30
olofk_I'll pull that in separately tonight when I can reach my computer05:33
olofk_I just noticed your ISE detection also. My plan was to just let the user source settings32/64, but I guess this has the added benefit that it won't pollute the environment after the build05:35
stekernit can probably be made a bit more bullet proof by checking that the detected directroy actually exist05:41
stekernand throw an error with a message asking the user to set --ise_path05:41
stekernif it doesn't05:42
olofk_I think we should check for the XILINX env to begin with in case the user has already sourced the correct settings file05:50
stekernyeah, that might be a good idea05:53
olofk_Found todays first good news story :)
stekerntodays date doesn't make me at all suspicous ;)06:01
stekernbut to be frank, apple have already went down the road with oddly shaped PCBs, that are visible to the user06:02
olofk_oh god. I have tried so hard to forget all the clear plastic items of the late 90's06:09
olofk_Everyone seemed to think it was a good idea to show off their PCBs at that time06:10
stekernyeah, I never appreciated that06:20
stekernand I remember that I never liked the G3 design, it looked like a vacuum cleaner06:21
olofk_stekern _franck__ I'm considering a fusesoc 1.1 (or 1.2 perhaps) release when the ISE support and VHDL bits are in place. Anything else that should go in that release?06:26
stekernqsys support? ;)06:31
olofk_Ok, but only because it's you ;)06:32
_franck_web_stekern: thanks, I'll do that when I come back home06:57
_franck_web_I wrote such a long answer to that guy on the opencores forum about his de1 and it just got lost :(07:33
olofk__franck_web_: That sucks :( I always copy the text before I press the submit button. It's a really crap forum on OpenCores08:39
_franck_web_I also use the "copy before push the button technique" :) but not this time08:43
_franck__stekern: sometimes it hangs, sometimes not12:14
_franck__here is a waveform I just captured:
stekernhmmm, why doesn't the ctrl_mtpr_ack_o go high there?12:20
_franck__I'll capture spr_group_present12:23
_franck__but yes, it is strange12:23
stekernI bet it has to do with this:
stekernbecause, isn't it to the dtlb sprs it tries to write?12:28
stekernthere's a similar hack in the fetcher for the itlbs12:28
_franck__AFAIR it is dtlb12:29
stekernlooking closer, the condition seems to be fulfilled by the '| spr_bus_we_i' though12:30
_franck__it access data cache spr12:31
_franck__DC Block Flush register12:32
_franck__I need to watch spr signals at mor1kx_dcache12:33
stekernyes, that might be more fragile...12:34
_franck__ok, see you in 20 minutes ;)12:35
stekernthere was this:
stekernthat should improve it, but there migh be issues with it still12:36
_franck__I'll tell you more tonight12:40
olofk_That patch could have benefited from some whit space cleanup12:40
olofk_ah.. or is it a different logic depth12:41
stekernyes, but I didn't like that it was munged together with that patch13:01
stekernbut made an exception and merged it anyway13:01
stekernI did that as: case()...endcase; if (rst) set_some_signal;13:05
stekerninstead of: if (rst) set_some_signal else case()...endcase13:06
stekernI usually prefer: a=1; if (cond) a=0;13:07
stekernover: if (cond=0) a=0 else a=1;13:08
olofk_me too13:16
olofkrah: That was surprisingly fun. I have to show that to my daughter when she's slightly older17:42
analognoiseHey OpenRisc!17:46
-!- olofk is now known as OpenRisc17:50
OpenRiscHey analognoise17:50
-!- OpenRisc is now known as olofk17:50
olofk_franck__: I hadn't seen this one before You're famous :)18:19
_franck__olofk: yeah I saw that one by accident while I was searching thing about openocd :)19:32
olofk_franck__: Same here :)19:37
olofkI only find videos of myself when I search for "dirty sluts" :(19:38
_franck__I pushed the patch for vhdl section19:40
olofk_franck__: No need for "if self.src_files:"19:45
olofkOtherwise everything looks good. I'll remove that line and push it, ok?19:46
_franck__because it is mandatory ? Just copied it...19:46
_franck__okay thanks, I'm working on something else right now19:46
olofkHmm.. it seems like I can't pull orpsoc-cores anymore19:54
olofkDid stekern remove my access rights? :)19:54
olofkhmm... git pull -v shows me that it's stuck at "remote: Compressing objects:   4% (1/21)"20:00
olofkDamn... I managed to get 71% before it got stuck, but now I'm down at 9%20:16
raholofk: glad you liked it :-)20:36
olofkRemoved some local changes and now I can pull it.20:45
olofkspartan6 lx9 is not a big FPGA21:03
_franck__olofk: do you remember I had problem with https access access from fusesoc at work ?21:07
_franck__I think it is the solution:
_franck__I do have a proxy21:08
_franck__and it does https over http I think (from what I've read)21:08
olofkNetworks can be way too complicated21:10
_franck__I agree. "Are you sure this a proxy which is accessed by https, or rather a proxy that21:10
_franck__supports CONNECT"21:10
_franck__I have the second one21:10
_franck__I have to fix this if I want to hack from my dayjob !21:11
olofkSo that code would have to be in fusesoc to support your kind of connection21:12
_franck__I think so I didn't do any tests yet21:13
olofkThat's like 50% of the whole fusesoc code base :)21:13
olofkYeah, I'm ok with bringing it in if it solves problems, but I know next to nothing about proxies, so you and other people with proxies will have to do the testing21:14
olofkTime to sleep now. VHDL support pushed if you didn't see that, btw21:14
_franck__I don't know much either21:14
_franck__ok, gn21:14
_franck__verilog question. I would like to have a parameter of a instantiated module inside a generate loop to be dependent of my genvar.22:09
_franck__it does work22:10
_franck__however, as soon as I try to make it look better, I get The expression for a parameter actual associated with the parameter name ('BUF_WIDTH') for the module instance ('wb_port') must be constant.22:10
analognoise_franck__: If your work has a proxy (but you have internet access) you can get the proxy items from internet explorer23:05
--- Log closed Wed Apr 02 00:00:47 2014

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