IRC logs for #openrisc Tuesday, 2014-03-25

--- Log opened Tue Mar 25 00:00:35 2014
stekern_franck__: what ddr controller are you using? and what and how are you connecting to it other than the vga_lcd controller04:32
stekernbut, yes, it's bandwidth hungry. it puts some demands on the controller.04:37
stekernthat's actually the reason why I initially wrote the wb_sdram_ctrl, the versatile sdram controller wasn't fast enough for the vga_lcd04:38
stekernblueCmd: I got the mail from fsf now06:05
_franck__stekern: I used your wb_sdram_ctrl arbiter/cache and wrapped the altera ddr2 controller behind it07:04
_franck__plus some hacks here in there to make it works07:05
_franck__the problem is the configured burst size on the ddr controller size I know ask for 8 bytes at a time but it should be much more to be efficient07:06
stekernah, yes... I know, I have the same problem on the sockit board07:10
stekern...and I've also noticed that it works better with or1200 than with mor1kx... simply because or1200 is so slow, so there's more bw over for the vga controller07:12
stekernso a smarter arbiter would be needed too07:13
_franck__there is 1MB of SSRAM on the board. I think I'll put the frame buffer here (need to go down to 16bpp to fit in)07:16
stekernyes, that's ideal07:18
stekernthe only problem with that is, I don't think the Linux driver can handle the case where the fb is at some predefined address07:19
stekernthat's easily hackable though07:19
_franck__ah ok, I need to check07:20
stekernhas anyone been using ksz8041nl(i) phys?07:26
stekernI'm having endless problems with them...07:28
stekern_franck__: but even with the SSRAM, you're not free from problems, you'll still have the cpu writing to the fb07:31
stekernother data and instructions are of course removed from the equation07:32
blueCmdstekern: excellent!08:40
stekernis it "normal" that auto-mdi/mdix can get confused and take around ~1 minute to figure things out11:09
venom00uthi, I'm using gdb from trunk, I load an executable with debug symbols but when I try to give `list main` I get an empty response11:48
stekernvenom00ut: or32-gdb or or1k-gdb?12:04
venom00utstekern, or1k-elf-gdb, anyways the debug information are missing in the binary itself for some reason, it's a probably a fault of clang, I'll investigate that better12:06
stekernah, ok, you should have mentioned that you are using clang/llvm12:07
stekerndebug info is indeed a missing feature there12:07
venom00utyep, I realised later they were actually missing in the binary12:09
olofkblueCmd: Jesus christ. You were not kidding when you said that is bad13:17
olofkstekern: Just read about using -- to delimit what arguments the parser eats. That's great. Didn't know13:30
stekernI found out by accident, just tried it out of habit13:37
blueCmdolofk: haha, no - it's horrible13:54
jungmawhen I convert the elf generated by or1k-elf-gcc with or1k-elf-objcopy -O binary  a.out a.bin I get big endian, but for my purpose i need little endian, how can I change that?14:04
olofkjungma: Aha! You're one of those little endians!14:06
olofkjungma: Out of curiousity. Why do you need little endian?14:07
olofkblueCmd: What backends does beep support?14:10
jungmaolofk: I want to put it in a TLM memory in Synopsys' Platform Architect and it seems that the endianess is wrong14:20
jungmabut maybe I'm just confused :D14:25
olofkjungma: Don't think I have any useful input there unfortunately14:26
olofkWe had a discussion about a week ago and wondered why people were asking for little endian versions of OpenRISC, so I just had to ask :)14:27
jungmaolofk: I think that the byte order is wrong14:29
jungmawhen I disassemble the code i get:14:30
jungma     100:       18 00 00 00     l.movhi r0,0x014:30
jungmabut at my TLM transactor I receive 0x1814:30
jungmaby the way, are some of you guys at DATE14? :)14:31
blueCmdolofk: I don't know, it appears to be writing some things to the TTY FD using ioctl14:35
blueCmdso it's a kernel driver for the PC speaker I'd guess14:35
blueCmdyou could probably GPIO it14:35
olofkjungma: Hadn't seen date before. Looks like an interesting conference14:48
_franck_web_I have a problem with github access with fusesoc. I don't know if the problem is coming from my python installation or from my local network14:51
_franck_web_this is what I have:
_franck_web_I can get the file with wget but getting it with urllib.urlretrieve gives me a "bad request"14:52
jungmaolofk: yap, it's a must be at our chair :D14:54
olofk_franck_web_: I remember someone at orconf who had problems with https accesses with his python installation15:20
olofkCould that be the problem?15:21
_franck_web_may be. I did try this:
_franck_web_but it didn't solve the problem15:21
ulrichkIs anyone here familiar with the pipeline implementation of the OR1200?15:28
stekernulrichk: faintly, I know the mor1kx cappuccino one by heart rhough15:38
blueCmdstekern: pff, why? it's not like you wrote it or anything..15:38
ulrichkI am trying to understand the pipe - on the website (, it says it has 5 stages.15:39
ulrichkIn the verilog code, I can distinguish 4 stages (if, id, ex, wb)...15:39
ulrichkAnd then in fact, the register file write enable seems to go high in execute already, so I don't know what writeback really does.15:40
ulrichkSo basically, 3 stages left... any idea would be helpful15:41
stekernulrichk: afair, it's just 4 stages, so your observation there is correct15:46
stekernblueCmd: mostly, I shuffled around juliusb's code to my liking ;)15:57
ulrichkstekern: thanks, I will have a closer look on the regfile. Seems like the 1 cyc delay for reading is why we still need writeback as an extra stage.16:10
Findetonhi there21:44
Findetonwhy isn't the OpenRISC ASIC a kickstarter project?22:03
Findetonit would probably get funding in a week22:03
blueCmdFindeton: it was23:14
Findetonyeah, that is crowdfunding23:15
blueCmdas opposed to kickstarter?23:16
FindetonI'm just saying it needs more publicity and getting it into kickstarter could make a difference23:16
blueCmdwell, one could obviously try - but I think it's the wrong way around. publicity first and then ASICs23:16
blueCmdbut I might be wrong23:16
Findetonwhat I don't know is the frequency the ASICs would run23:18
Findetonmaybe 500Mhz?23:18
Findetonperhaps you can get near that with good fpgas, although that's more expensive per person if you already have ASICs23:19
blueCmdsure is23:20
blueCmdregarding the speed, that's just a question of money really23:24
blueCmdthe smaller process you can afford, the higher speed sort of23:24
--- Log closed Wed Mar 26 00:00:37 2014

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