IRC logs for #openrisc Sunday, 2013-10-13

--- Log opened Sun Oct 13 00:00:37 2013
olofkLooks like the good ol' internet is freaking out over jor1k. Never seen my twitter feed this active07:27
stekernolofk: I'm having problems with wb_bfm_master and classic cycles07:50
stekernit doesn't assert stb and the wait_for_ack task seems suspiciously empty07:51
stekernhmm, looking a bit closer, I think the write task should call next, not wait_for_ack07:54
stekernand wait_for_ack can be completely removed07:55
stekernseems to work at least, but I'd prefer it if you'd confirm it before I send a patch07:55
olofkstekern: Oh, sorry. Forgot to say that I never implemented classic mode completely :(08:04
olofkhaven't looked at the code fo08:05
olofkr a while, but IIRC I rewrote some parts so wait_for_ack shouldn't be needed08:06
stekernok, then my gut-feel with exchange wait_for_ack with next was probably right08:08
olofkanother thing that is not implemented is deasserting stb during a transaction08:08
stekernI'll test it some more and if nothing seems broken I'll send a patch08:09
stekernwhy would I want to deassert stb during a transaction?08:09
olofksay you're reading a data block from an async fifo. FIFO might be occasionally empty, so deasserting stb pauses the transaction08:10
olofkAt least I think that what it's for. Never actually seen it used outside of the spec08:11
olofkHence not implemented yet :)08:11
stekernhmm.. yeah, but then it's the slave's job to insert wait-states by not asserting ack08:11
stekernor do you mean a fifo on the master side, that it reads from and do writes out on the wb bus?08:12
stekern...I'm not going to need that right now anyway ;)08:13
stekernI just want to write some simple registers to setup my synth08:14
stekernwhy do you need the Tp btw?08:15
olofkYou shouldn't need that. I used it mostly for debugging the BFM when I had delta-cycle problems08:16
olofkOh... it's a localparam. That should perhaps be a parameter08:19
stekernso, it turned out to be a wise choice to use orpsoc to drive the simulstions of my synth, we alreadt have killed two bugs in wb_bfm ;)08:24
olofkBut you're right. It's great to get as much tsting as possible on these things09:11
rfajardomorning everyone09:32
rfajardoI have written a small recipe to compile the current newlib toolchain for OSX Mountain Lion.09:32
rfajardoWhere should I put it in?09:32
rahare these here development boards12:08
rahever going to be back in stock?12:08
stekernrah: you've probably got a better chance getting an answer to that by contacting orsoc by e-mail12:18
rahI'd like to try running an openrisc computer12:34
rahare there any other FPGA boards that are known-to-work/recommended/liked?12:34
rahand in particular, with FPGAs that can be programmed using free software?12:35
rah(do any FPGAs exist that can be programmed using free software?)12:35
stekernrfajardo: great! could you add that to the wiki along with the "normal" recipe?12:39
stekernrah: there are several other boards that have been "openrisc proven", whixh one to choose depends on your requirements. but, de0 nano is a widely used board12:41
rahthis looks cool but from what I can tell, the Altera chips need proprietary software12:42
stekernyes, but the answer to youf second question is: no12:42
rahstekern: yeah I looked at the de0 nano but it doesn't seem have any usable I/O12:43
stekerndefine usable i/o, it have loads of exposed fpga pins on pinheaders12:43
stekernwhat board did you link to? cant copy-paste from my phone12:44
rahthe board I linked to is the "Cyclone V GX Starter Kit"12:45
rahit has Arduino headers, which means an SPI bus, to which one might attach a USB host contoller and then keyboard/mouse/video12:45
rahI'm labouring under the impression that trying to connect a USB host using GPIO bit-banging would be a Bad Idea(tm)12:46
stekernok, that seems pretty good for the price, it's certainly possible to run openrisc on it, but atm we don't have any board ports for it12:47
stekern"all" pins on an Fpga is "gpio"12:48
rahI see12:49
stekernyou probably need to read up a bit more on fpgas, me thinks12:49
stekernyou can connect spi or video to de0 nanos headers12:50
rahdo you know if anybody *has* connected a USB host controller to a de0 nano?12:51
stekernif you just need usb for kbd/mouse it's probably easier to use ps212:52
rahwhat about video though?  I was thinking of those nice USB video adapters supported by X (whose name I forget)12:54
rahthat's the ones12:55
stekernnormal vfa is probavly easier...12:55
stekernI've got an 4" lcd connected to my de0 nano12:56
* rah googles "VFA" :-)12:56
stekerns/vfa/vga ;)12:56
rahdid you eman "VGA"?12:56
rahright :-)12:56
rahwhat kind of bandwidth would the board support with VGA?12:57
stekernhard to write with the on-screen kb..12:57
rahwhat kind of maximum resolution/refresh-rate would you expect to get?12:59
* rah is betting low12:59
stekern800x600 works at least13:01
* rah decides a de0 nano would be a good starting point13:06
rahthanks for answering my questions :-)13:06
rfajardorah, I believe Xilinx FPGAs can be programmed using xc3sprog.13:17
stekernrfajardo: great! could you add that to the wiki along with the "normal" recipe?13:19
stekernto your osx thing13:20
rfajardoOpencores wiki?13:20
rfajardosure thing13:20
stekernyes, you can probably program altera fpgas using free tools too, but not build the image13:21
stekernyes, the opencores wiki13:22
nvmindrfajardo: are you the one behind minsoc?13:22
rfajardonvmind, Maybe I'm ahead of it now. But you could say that.13:23
nvmindcan I ask you some question? I have some strange error with adv_debug_sys and I am using a set up that is pratically identical to the one you built on minsoc13:24
rfajardoYup, bring it.13:25
rahstekern: I'm looking at the electrical specifications of PS/2 ports and it says the data lines are 5V whereas the GPIO ports on the de0 nano are 3.3V13:25
nvmindI am trying to simulate with icarus through vpi a debugging session13:26
rfajardostekern, it includes a patch to or1k-src. Maybe pgavin could put it in.13:26
stekernit'll work with 3.3V13:26
nvmindwhen I connect with gdb I get a CRC error13:26
rfajardostekern, it is a really small one.13:26
stekernI can put it in, post it to the ml13:27
rfajardostekern, what is ml?13:29
rfajardomailing list :P13:29
nvmindtarget remote :999913:37
nvmindRemote debugging using :999913:37
nvmindRemote failure reply: E0113:37
nvmindError while reading all registers: 'CRC mismatch'13:38
nvmindWarning: Failed to write to RSP client: Closing client connection: Broken pipe13:38
nvmindWarning: Attempt to write '0' to unopened RSP client: Ignored13:38
nvmindWarning: Attempt to write '1' to unopened RSP client: Ignored13:38
nvmindWarning: Attempt to write '#' to unopened RSP client: Ignored13:38
nvmindWarning: Attempt to write 'a' to unopened RSP client: Ignored13:38
nvmindWarning: Attempt to write '6' to unopened RSP client: Ignored13:38
nvmindWarning: Attempt to read from unopened RSP client: Ignored13:38
nvmind 13:38
nvmindsorry :) for the cut and paste13:38
nvmindrfajardo: any idea?13:38
nvmindI have checked the connection between modules a thousand times :) and they looks identical between my soc and yours.13:40
nvmindthe software layer works perfectly with minsoc13:40
rfajardothis is between gdb and adv_jtag_bridge?13:45
rfajardostekern, email sent13:45
nvmindrfajardo: first three rows are from gdb13:46
nvmindthe rest is from adv_jtag_bridge13:46
rfajardodid you compile RSP into adv_jtag_bridge?13:48
nvmindmmm RSP?13:49
nvmindok remote server protocol ;)13:53
nvmindwell no...13:54
nvmindI was wrong... it is enabled by default13:59
nvmindso yes it is enabled13:59
rfajardowhat is the output when you run adv_jtag_bridge?14:11
rfajardowhich gdb are you using?14:11
nvmindI have the same results with gdb 6.8 from minsoc and mine that is GNU gdb (GDB)
nvmind 14:12
nvmindthis is the complete output from adv_jtag_bridge14:14
nvmindand this is the self test14:16
nvmindself test gives the same results on minsoc (at least the version I checked out)14:17
rfajardoit does not seem that your FPGA is correctly configured.14:18
rfajardoadv_jtad_bridge does not find the Openrisc.14:19
nvmindI am not on fpga14:19
rfajardothat's correct :P14:19
rfajardois your icarus verilog simulation running?14:19
nvmindjust simulating :)14:19
nvmindnot that stupid ;)14:20
rfajardoI'm sorry14:20
nvminddon't worry14:20
rfajardoyou know, you have to follow the script. Sometimes I wasn't simulating myself and was wondering what the heck was going on.14:21
nvmindI can understand why you are asking me this questions14:21
rfajardoor1200 release?14:21
nvmindI bet :)14:21
nvmindI took it from opencore svn14:22
nvmindbad thing? :)14:22
stekernrfajardo: nice, a git formatted patch with the change in configure as well would have been easier to apply though14:29
stekern(yes I'm lazy)14:29
stekernit also have the benefit of preserving the authorship14:30
rfajardonot necessarily, I do the same for minsoc trunk.14:30
rfajardoneed a time14:30
rfajardoI'm watching something. Back in 5 min. Stekern, should I try again? Or are you done?14:31
nvmindstekern: git is amazing ;) I have just converted the HLS team in my university to git14:32
stekernno, I'm a bit caught up in other things right now, but if you could do that it'd be great14:32
stekernI also wonder if that'd be something upstream would be interested in, since it's not really openrisc specific14:32
stekernbut I'd be happy to apply it locally anyway14:33
stekernand with locally I mean openrisc/or1k-src14:34
rfajardosorry guys, I'm back14:37
rfajardostekern, my git is not even configured. Let me do that.14:38
rfajardoWiki is ready. I tell you guys when I'm ready to send the patch in.14:39
rfajardonvmind, I don't know exactly what is wrong. I've heard adv_debug_sys does not work with caches. Take a look at Example 2. It might be the same error you're experiencing.14:42
rfajardonvmind, some guys seem to have had good experiences with openocd instead of adv_jtag_bridge. Still adv_debug_sys hardware.14:42
* rah suddenly Gets It15:00
rahis there a USB host controller core on opencores? :-)15:00
rahit would appears so :-)15:02
rahhow many cells does an openrisc core take up on an altera FPGA?16:03
_franck_nvmind: did you try openocd / jtag_vpi ?16:09
juliusbrah it depends _a lot_ on the configuration16:21
juliusbcould be from a few thousand logic cells and a couple hundred FFs up to several thousand logic cells and several hundred FFs16:22
* rah notices
* rah decides perhaps the de0 nano isn't the best starting point16:38
rahis this the list of boards supported by orpsoc v3?16:43
rahif not, is there such a list?16:43
rfajardoI have tried a <git send-email -1>. Let's see where it goes to. So far no email.16:46
_franck_rah: there is no list. However, you can find supported boards here16:48
rah_franck_: thanks16:51
rfajardogit send-email failed because of osx stuff… better luck next time17:00
rfajardosee you guys17:00
poke53281olofk: Yes, yesterday jor1k got a Phoronix and a slashdot article.17:06
poke53281But not more than 5300 visits.17:13
poke53281And only asks why 63MB of RAM ;)17:33
poke53281And only one asks ....17:42
rahis there anything preventing a free FPGA design?18:32
knzmany patents18:37
rahugh :-(18:37
rahwould that really be a problem?18:37
knzhow do you mean?18:37
rahthere are many software patents but people still write free software18:38
knzsoftware patents are a recent thing, and rarely enforced around the world18:38
knzsoftware is protected mainyl by copyright, which means copy is a problem but rewriting from sratch to achieve the same funcitonality is OK18:38
knzthis is what made open source possible18:38
knzwith ahrdware the picture is entirely different18:39
rahhow so?18:39
rahI note that, in fact there is a free FPGA core project here:,fpga18:39
knzwell for one there are not so many ways to arrange silicon gates to make programmable basic elements18:39
knzmost of them are patented already18:39
knz(the project you link to is in "planning" phase since 2009, which means it's vaporware)18:40
rah"most" but not all ?18:40
knzthe others that are know are inefficient18:40
knzspace- and energy-wise18:40
rahI see18:40
knzthe first fpga patents are due to expire this decade18:40
knzso there is hope18:41
rahdo you know which year exactly, just out of curiosity?18:42
nvmind_franck_: nope. but I am on the way of trying it19:34
_franck_stekern: didn't you need that to make your FB works ?21:36
_franck_I needed to signal tap it :)21:37
_franck_BTW, this is how I use signal tap after download the kernel with openocd: I add a mdelay(10000) before the piece of code I want to have in signal tap21:39
_franck_after I reach this delay, I just shut down openocd and start signal tap trigger...21:40
astarThe ARM world seens to want to go to optimizing GPU performance?21:45
--- Log closed Mon Oct 14 00:00:39 2013

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