| --- Log opened Sun Oct 13 00:00:37 2013 | ||
| olofk | Looks like the good ol' internet is freaking out over jor1k. Never seen my twitter feed this active | 07:27 |
|---|---|---|
| stekern | olofk: I'm having problems with wb_bfm_master and classic cycles | 07:50 |
| stekern | it doesn't assert stb and the wait_for_ack task seems suspiciously empty | 07:51 |
| stekern | hmm, looking a bit closer, I think the write task should call next, not wait_for_ack | 07:54 |
| stekern | and wait_for_ack can be completely removed | 07:55 |
| stekern | seems to work at least, but I'd prefer it if you'd confirm it before I send a patch | 07:55 |
| olofk | stekern: Oh, sorry. Forgot to say that I never implemented classic mode completely :( | 08:04 |
| olofk | haven't looked at the code fo | 08:05 |
| olofk | r a while, but IIRC I rewrote some parts so wait_for_ack shouldn't be needed | 08:06 |
| stekern | ok, then my gut-feel with exchange wait_for_ack with next was probably right | 08:08 |
| olofk | another thing that is not implemented is deasserting stb during a transaction | 08:08 |
| stekern | I'll test it some more and if nothing seems broken I'll send a patch | 08:09 |
| olofk | Great | 08:09 |
| stekern | why would I want to deassert stb during a transaction? | 08:09 |
| olofk | say you're reading a data block from an async fifo. FIFO might be occasionally empty, so deasserting stb pauses the transaction | 08:10 |
| olofk | At least I think that what it's for. Never actually seen it used outside of the spec | 08:11 |
| olofk | Hence not implemented yet :) | 08:11 |
| stekern | hmm.. yeah, but then it's the slave's job to insert wait-states by not asserting ack | 08:11 |
| stekern | or do you mean a fifo on the master side, that it reads from and do writes out on the wb bus? | 08:12 |
| olofk | exactly | 08:12 |
| stekern | ok | 08:13 |
| stekern | ...I'm not going to need that right now anyway ;) | 08:13 |
| stekern | I just want to write some simple registers to setup my synth | 08:14 |
| stekern | why do you need the Tp btw? | 08:15 |
| olofk | You shouldn't need that. I used it mostly for debugging the BFM when I had delta-cycle problems | 08:16 |
| olofk | Oh... it's a localparam. That should perhaps be a parameter | 08:19 |
| stekern | so, it turned out to be a wise choice to use orpsoc to drive the simulstions of my synth, we alreadt have killed two bugs in wb_bfm ;) | 08:24 |
| olofk | haha | 08:59 |
| olofk | But you're right. It's great to get as much tsting as possible on these things | 09:11 |
| olofk | Later | 09:15 |
| rfajardo | morning everyone | 09:32 |
| rfajardo | I have written a small recipe to compile the current newlib toolchain for OSX Mountain Lion. | 09:32 |
| rfajardo | Where should I put it in? | 09:32 |
| nvmind | hello | 11:09 |
| rah | are these here development boards | 12:08 |
| rah | http://opencores.org/shop,item,11 | 12:08 |
| rah | ever going to be back in stock? | 12:08 |
| stekern | rah: you've probably got a better chance getting an answer to that by contacting orsoc by e-mail | 12:18 |
| rah | ok | 12:33 |
| rah | I'd like to try running an openrisc computer | 12:34 |
| rah | are there any other FPGA boards that are known-to-work/recommended/liked? | 12:34 |
| rah | and in particular, with FPGAs that can be programmed using free software? | 12:35 |
| rah | (do any FPGAs exist that can be programmed using free software?) | 12:35 |
| stekern | rfajardo: great! could you add that to the wiki along with the "normal" recipe? | 12:39 |
| rah | http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=167&No=830&PartNo=3 | 12:41 |
| stekern | rah: there are several other boards that have been "openrisc proven", whixh one to choose depends on your requirements. but, de0 nano is a widely used board | 12:41 |
| rah | this looks cool but from what I can tell, the Altera chips need proprietary software | 12:42 |
| stekern | yes, but the answer to youf second question is: no | 12:42 |
| rah | stekern: yeah I looked at the de0 nano but it doesn't seem have any usable I/O | 12:43 |
| rah | :-( | 12:43 |
| stekern | define usable i/o, it have loads of exposed fpga pins on pinheaders | 12:43 |
| stekern | what board did you link to? cant copy-paste from my phone | 12:44 |
| rah | the board I linked to is the "Cyclone V GX Starter Kit" | 12:45 |
| rah | it has Arduino headers, which means an SPI bus, to which one might attach a USB host contoller and then keyboard/mouse/video | 12:45 |
| rah | I'm labouring under the impression that trying to connect a USB host using GPIO bit-banging would be a Bad Idea(tm) | 12:46 |
| stekern | ok, that seems pretty good for the price, it's certainly possible to run openrisc on it, but atm we don't have any board ports for it | 12:47 |
| rah | ok | 12:48 |
| stekern | "all" pins on an Fpga is "gpio" | 12:48 |
| rah | hmm | 12:49 |
| rah | I see | 12:49 |
| stekern | you probably need to read up a bit more on fpgas, me thinks | 12:49 |
| stekern | you can connect spi or video to de0 nanos headers | 12:50 |
| rah | ok | 12:50 |
| rah | do you know if anybody *has* connected a USB host controller to a de0 nano? | 12:51 |
| stekern | if you just need usb for kbd/mouse it's probably easier to use ps2 | 12:52 |
| rah | what about video though? I was thinking of those nice USB video adapters supported by X (whose name I forget) | 12:54 |
| rah | "Displaylink" | 12:55 |
| rah | that's the ones | 12:55 |
| stekern | normal vfa is probavly easier... | 12:55 |
| stekern | I've got an 4" lcd connected to my de0 nano | 12:56 |
| * rah googles "VFA" :-) | 12:56 | |
| stekern | s/vfa/vga ;) | 12:56 |
| rah | did you eman "VGA"? | 12:56 |
| rah | right :-) | 12:56 |
| rah | what kind of bandwidth would the board support with VGA? | 12:57 |
| stekern | hard to write with the on-screen kb.. | 12:57 |
| rah | what kind of maximum resolution/refresh-rate would you expect to get? | 12:59 |
| * rah is betting low | 12:59 | |
| stekern | 800x600 works at least | 13:01 |
| rah | mmm | 13:01 |
| * rah decides a de0 nano would be a good starting point | 13:06 | |
| rah | thanks for answering my questions :-) | 13:06 |
| rfajardo | rah, I believe Xilinx FPGAs can be programmed using xc3sprog. | 13:17 |
| stekern | rfajardo: great! could you add that to the wiki along with the "normal" recipe? | 13:19 |
| stekern | to your osx thing | 13:20 |
| rfajardo | Opencores wiki? | 13:20 |
| rfajardo | sure thing | 13:20 |
| stekern | yes, you can probably program altera fpgas using free tools too, but not build the image | 13:21 |
| stekern | yes, the opencores wiki | 13:22 |
| nvmind | rfajardo: are you the one behind minsoc? | 13:22 |
| rfajardo | nvmind, Maybe I'm ahead of it now. But you could say that. | 13:23 |
| nvmind | :) | 13:23 |
| nvmind | can I ask you some question? I have some strange error with adv_debug_sys and I am using a set up that is pratically identical to the one you built on minsoc | 13:24 |
| rfajardo | Yup, bring it. | 13:25 |
| rah | stekern: I'm looking at the electrical specifications of PS/2 ports and it says the data lines are 5V whereas the GPIO ports on the de0 nano are 3.3V | 13:25 |
| nvmind | I am trying to simulate with icarus through vpi a debugging session | 13:26 |
| nvmind | but | 13:26 |
| rfajardo | stekern, it includes a patch to or1k-src. Maybe pgavin could put it in. | 13:26 |
| stekern | it'll work with 3.3V | 13:26 |
| nvmind | when I connect with gdb I get a CRC error | 13:26 |
| rfajardo | stekern, it is a really small one. | 13:26 |
| stekern | I can put it in, post it to the ml | 13:27 |
| rah | mmm | 13:27 |
| rfajardo | stekern, what is ml? | 13:29 |
| rfajardo | mailing list :P | 13:29 |
| nvmind | target remote :9999 | 13:37 |
| nvmind | Remote debugging using :9999 | 13:37 |
| nvmind | Remote failure reply: E01 | 13:37 |
| nvmind | Error while reading all registers: 'CRC mismatch' | 13:38 |
| nvmind | Warning: Failed to write to RSP client: Closing client connection: Broken pipe | 13:38 |
| nvmind | Warning: Attempt to write '0' to unopened RSP client: Ignored | 13:38 |
| nvmind | Warning: Attempt to write '1' to unopened RSP client: Ignored | 13:38 |
| nvmind | Warning: Attempt to write '#' to unopened RSP client: Ignored | 13:38 |
| nvmind | Warning: Attempt to write 'a' to unopened RSP client: Ignored | 13:38 |
| nvmind | Warning: Attempt to write '6' to unopened RSP client: Ignored | 13:38 |
| nvmind | Warning: Attempt to read from unopened RSP client: Ignored | 13:38 |
| nvmind | 13:38 | |
| nvmind | sorry :) for the cut and paste | 13:38 |
| nvmind | rfajardo: any idea? | 13:38 |
| nvmind | I have checked the connection between modules a thousand times :) and they looks identical between my soc and yours. | 13:40 |
| nvmind | the software layer works perfectly with minsoc | 13:40 |
| rfajardo | this is between gdb and adv_jtag_bridge? | 13:45 |
| rfajardo | stekern, email sent | 13:45 |
| nvmind | rfajardo: first three rows are from gdb | 13:46 |
| nvmind | the rest is from adv_jtag_bridge | 13:46 |
| rfajardo | did you compile RSP into adv_jtag_bridge? | 13:48 |
| nvmind | mmm RSP? | 13:49 |
| nvmind | ok remote server protocol ;) | 13:53 |
| nvmind | serial* | 13:53 |
| nvmind | well no... | 13:54 |
| nvmind | I was wrong... it is enabled by default | 13:59 |
| nvmind | so yes it is enabled | 13:59 |
| rfajardo | what is the output when you run adv_jtag_bridge? | 14:11 |
| rfajardo | which gdb are you using? | 14:11 |
| nvmind | I have the same results with gdb 6.8 from minsoc and mine that is GNU gdb (GDB) 7.5.50.20121129-cvs | 14:12 |
| nvmind | 14:12 | |
| nvmind | http://nopaste.info/a21ec099a4.html | 14:13 |
| nvmind | this is the complete output from adv_jtag_bridge | 14:14 |
| nvmind | and this is the self test | 14:16 |
| nvmind | http://nopaste.info/a18b0e4b13.html | 14:16 |
| nvmind | self test gives the same results on minsoc (at least the version I checked out) | 14:17 |
| rfajardo | it does not seem that your FPGA is correctly configured. | 14:18 |
| rfajardo | adv_jtad_bridge does not find the Openrisc. | 14:19 |
| nvmind | I am not on fpga | 14:19 |
| rfajardo | that's correct :P | 14:19 |
| rfajardo | is your icarus verilog simulation running? | 14:19 |
| nvmind | just simulating :) | 14:19 |
| nvmind | ... | 14:20 |
| nvmind | :) | 14:20 |
| nvmind | not that stupid ;) | 14:20 |
| rfajardo | I'm sorry | 14:20 |
| nvmind | don't worry | 14:20 |
| nvmind | :) | 14:20 |
| rfajardo | you know, you have to follow the script. Sometimes I wasn't simulating myself and was wondering what the heck was going on. | 14:21 |
| nvmind | I can understand why you are asking me this questions | 14:21 |
| rfajardo | or1200 release? | 14:21 |
| nvmind | v2 | 14:21 |
| nvmind | I bet :) | 14:21 |
| nvmind | I took it from opencore svn | 14:22 |
| rfajardo | trunk? | 14:22 |
| nvmind | yes | 14:22 |
| nvmind | bad thing? :) | 14:22 |
| stekern | rfajardo: nice, a git formatted patch with the change in configure as well would have been easier to apply though | 14:29 |
| stekern | (yes I'm lazy) | 14:29 |
| stekern | it also have the benefit of preserving the authorship | 14:30 |
| rfajardo | not necessarily, I do the same for minsoc trunk. | 14:30 |
| rfajardo | need a time | 14:30 |
| rfajardo | I'm watching something. Back in 5 min. Stekern, should I try again? Or are you done? | 14:31 |
| nvmind | stekern: git is amazing ;) I have just converted the HLS team in my university to git | 14:32 |
| stekern | no, I'm a bit caught up in other things right now, but if you could do that it'd be great | 14:32 |
| stekern | I also wonder if that'd be something upstream would be interested in, since it's not really openrisc specific | 14:32 |
| stekern | but I'd be happy to apply it locally anyway | 14:33 |
| stekern | and with locally I mean openrisc/or1k-src | 14:34 |
| rfajardo | sorry guys, I'm back | 14:37 |
| rfajardo | stekern, my git is not even configured. Let me do that. | 14:38 |
| rfajardo | Wiki is ready. I tell you guys when I'm ready to send the patch in. | 14:39 |
| rfajardo | nvmind, I don't know exactly what is wrong. I've heard adv_debug_sys does not work with caches. Take a look at http://www.minsoc.com/advanced_jtag_bridge_faq#adv_jtag_bridge_self_test_fails Example 2. It might be the same error you're experiencing. | 14:42 |
| rfajardo | nvmind, some guys seem to have had good experiences with openocd instead of adv_jtag_bridge. Still adv_debug_sys hardware. | 14:42 |
| rfajardo | brb | 14:42 |
| * rah suddenly Gets It | 15:00 | |
| rah | is there a USB host controller core on opencores? :-) | 15:00 |
| rah | it would appears so :-) | 15:02 |
| rah | how many cells does an openrisc core take up on an altera FPGA? | 16:03 |
| _franck_ | nvmind: did you try openocd / jtag_vpi ? | 16:09 |
| juliusb | rah it depends _a lot_ on the configuration | 16:21 |
| juliusb | could be from a few thousand logic cells and a couple hundred FFs up to several thousand logic cells and several hundred FFs | 16:22 |
| rah | ok | 16:38 |
| rah | thanks | 16:38 |
| * rah notices http://opencores.org/or1k/FPGA_Development_Boards | 16:38 | |
| * rah decides perhaps the de0 nano isn't the best starting point | 16:38 | |
| rah | is this the list of boards supported by orpsoc v3? | 16:43 |
| rah | if not, is there such a list? | 16:43 |
| rfajardo | I have tried a <git send-email -1>. Let's see where it goes to. So far no email. | 16:46 |
| _franck_ | rah: there is no list. However, you can find supported boards here | 16:48 |
| _franck_ | https://github.com/openrisc/orpsoc-cores/tree/master/systems | 16:48 |
| rah | _franck_: thanks | 16:51 |
| rfajardo | git send-email failed because of osx stuff… better luck next time | 17:00 |
| rfajardo | see you guys | 17:00 |
| poke53281 | olofk: Yes, yesterday jor1k got a Phoronix and a slashdot article. | 17:06 |
| poke53281 | http://tech.slashdot.org/story/13/10/12/1819231/javascript-based-openrisc-emulator-can-run-linux-gcc-wayland | 17:07 |
| poke53281 | http://www.phoronix.com/scan.php?page=news_item&px=MTQ4NDI | 17:07 |
| poke53281 | But not more than 5300 visits. | 17:13 |
| poke53281 | And only asks why 63MB of RAM ;) | 17:33 |
| poke53281 | And only one asks .... | 17:42 |
| rah | is there anything preventing a free FPGA design? | 18:32 |
| knz | patents | 18:37 |
| knz | many patents | 18:37 |
| rah | ugh :-( | 18:37 |
| rah | would that really be a problem? | 18:37 |
| knz | how do you mean? | 18:37 |
| rah | there are many software patents but people still write free software | 18:38 |
| knz | huh | 18:38 |
| knz | software patents are a recent thing, and rarely enforced around the world | 18:38 |
| knz | software is protected mainyl by copyright, which means copy is a problem but rewriting from sratch to achieve the same funcitonality is OK | 18:38 |
| knz | this is what made open source possible | 18:38 |
| knz | with ahrdware the picture is entirely different | 18:39 |
| rah | how so? | 18:39 |
| rah | I note that, in fact there is a free FPGA core project here: http://opencores.org/project,fpga | 18:39 |
| knz | well for one there are not so many ways to arrange silicon gates to make programmable basic elements | 18:39 |
| knz | most of them are patented already | 18:39 |
| rah | ah | 18:40 |
| knz | (the project you link to is in "planning" phase since 2009, which means it's vaporware) | 18:40 |
| rah | "most" but not all ? | 18:40 |
| knz | well | 18:40 |
| knz | the others that are know are inefficient | 18:40 |
| knz | space- and energy-wise | 18:40 |
| rah | I see | 18:40 |
| knz | BUT | 18:40 |
| knz | the first fpga patents are due to expire this decade | 18:40 |
| knz | so there is hope | 18:41 |
| rah | cool | 18:41 |
| rah | do you know which year exactly, just out of curiosity? | 18:42 |
| knz | nope | 18:42 |
| nvmind | _franck_: nope. but I am on the way of trying it | 19:34 |
| _franck_ | stekern: http://pastie.org/8400009 didn't you need that to make your FB works ? | 21:36 |
| _franck_ | I needed to signal tap it :) | 21:37 |
| _franck_ | BTW, this is how I use signal tap after download the kernel with openocd: I add a mdelay(10000) before the piece of code I want to have in signal tap | 21:39 |
| _franck_ | after I reach this delay, I just shut down openocd and start signal tap trigger... | 21:40 |
| astar | Toolchain? | 21:41 |
| astar | The ARM world seens to want to go to optimizing GPU performance? | 21:45 |
| --- Log closed Mon Oct 14 00:00:39 2013 | ||
Generated by irclog2html.py 2.15.2 by Marius Gedminas - find it at mg.pov.lt!