IRC logs for #openrisc Saturday, 2013-10-12

--- Log opened Sat Oct 12 00:00:36 2013
poke53281Good news. According to an email I get a Phoronix article tomorrow. Suggestions welcome to improve the website and to promote the opencores project.00:31
poke53281And please, no blinking banner advertisment across the screen with 3 different close buttons at which only one is correct.00:47
poke53281http://s-macke.github.io/jor1k/02:52
poke53281Finally the website looks a little bit better02:52
nvmindhi13:50
nvmindI am developing a SoC as part of my thesis and I am at the point that a little test program is running correctly in simulation13:57
nvmindI decided to try to simulate the condition in which I load the program to be executed using gdb and the adv_debug_sys13:58
nvmindbut when I try to connect to the bridge with gdb I got a CRC ERROR14:00
nvmindsaying that match bit after write is 0.14:00
nvmindAny idea on the reason?14:01
nvmindmy set up is pratically identical to the one in minsoc14:01
nvmind(with the only difference that mine is not working :) )14:04
juliusbnvmind: hi, what are you actually attaching to the RTL model to drive the JTAG pins?14:41
juliusbpoke53281: that is a substantial facelift :)14:42
nvmindjuliusb: dbg_comm_vpi15:03
stekernI think I have a nice little wb accessable synth draft cooked up now15:07
stekernno envelopes nor fiƶters, but velocity and polyphony should work15:08
stekerntime for testbench writing, to see if it actually work15:09
stekernI wonder what would be the best to verify functionality though...15:10
stekernit's not trivial to determine that the output is correct, at least not automatically15:11
juliusbnvmind: is that something which is bundled with the adv_debug_sys? I'm not 100% familiar with it15:56
nvmindyes16:07
stekernI think _franck_ have been using some other vpi setup together with adv_debug_sys16:17
nvmindhttp://www.mail-archive.com/openocd-devel@lists.sourceforge.net/msg04473.html16:28
nvmindI found this...16:29
nvmindso he is using openocd16:29
stekernyes, I think most of us are16:30
nvmindwell I'll give it a try16:33
nvminddo I need any particular version of adv_debug_sys or or1200?16:33
PowermaniacAnyone in here awake and able to check something with there hopefully awake eyes?17:46
PowermaniacAs I'm either going crazy or ##programming doesn't see what I see...17:46
PowermaniacIt relates to #openrisc in a way as it is talking about logic gates basically but using it in Python17:48
PowermaniacAll good, I was just going blind17:54
--- Log closed Sun Oct 13 00:00:37 2013

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