| --- Log opened Sat Oct 12 00:00:36 2013 | ||
| poke53281 | Good news. According to an email I get a Phoronix article tomorrow. Suggestions welcome to improve the website and to promote the opencores project. | 00:31 |
|---|---|---|
| poke53281 | And please, no blinking banner advertisment across the screen with 3 different close buttons at which only one is correct. | 00:47 |
| poke53281 | http://s-macke.github.io/jor1k/ | 02:52 |
| poke53281 | Finally the website looks a little bit better | 02:52 |
| nvmind | hi | 13:50 |
| nvmind | I am developing a SoC as part of my thesis and I am at the point that a little test program is running correctly in simulation | 13:57 |
| nvmind | I decided to try to simulate the condition in which I load the program to be executed using gdb and the adv_debug_sys | 13:58 |
| nvmind | but when I try to connect to the bridge with gdb I got a CRC ERROR | 14:00 |
| nvmind | saying that match bit after write is 0. | 14:00 |
| nvmind | Any idea on the reason? | 14:01 |
| nvmind | my set up is pratically identical to the one in minsoc | 14:01 |
| nvmind | (with the only difference that mine is not working :) ) | 14:04 |
| juliusb | nvmind: hi, what are you actually attaching to the RTL model to drive the JTAG pins? | 14:41 |
| juliusb | poke53281: that is a substantial facelift :) | 14:42 |
| nvmind | juliusb: dbg_comm_vpi | 15:03 |
| stekern | I think I have a nice little wb accessable synth draft cooked up now | 15:07 |
| stekern | no envelopes nor fiöters, but velocity and polyphony should work | 15:08 |
| stekern | time for testbench writing, to see if it actually work | 15:09 |
| stekern | I wonder what would be the best to verify functionality though... | 15:10 |
| stekern | it's not trivial to determine that the output is correct, at least not automatically | 15:11 |
| juliusb | nvmind: is that something which is bundled with the adv_debug_sys? I'm not 100% familiar with it | 15:56 |
| nvmind | yes | 16:07 |
| stekern | I think _franck_ have been using some other vpi setup together with adv_debug_sys | 16:17 |
| nvmind | http://www.mail-archive.com/openocd-devel@lists.sourceforge.net/msg04473.html | 16:28 |
| nvmind | I found this... | 16:29 |
| nvmind | so he is using openocd | 16:29 |
| stekern | yes, I think most of us are | 16:30 |
| nvmind | well I'll give it a try | 16:33 |
| nvmind | do I need any particular version of adv_debug_sys or or1200? | 16:33 |
| Powermaniac | Anyone in here awake and able to check something with there hopefully awake eyes? | 17:46 |
| Powermaniac | As I'm either going crazy or ##programming doesn't see what I see... | 17:46 |
| Powermaniac | It relates to #openrisc in a way as it is talking about logic gates basically but using it in Python | 17:48 |
| Powermaniac | All good, I was just going blind | 17:54 |
| --- Log closed Sun Oct 13 00:00:37 2013 | ||
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