IRC logs for #openrisc Friday, 2013-10-11

--- Log opened Fri Oct 11 00:00:34 2013
hansfbaierAre the conference slides already online?02:37
-!- Netsplit *.net <-> *.split quits: bentley`02:44
stekernjuliusb: I agree, that's really cool and solves the problem of simulation not easily being made parallell06:32
stekernin an interesting way06:32
olofkhi07:40
stekernmorning olofk07:40
jeremybennettmorning all07:43
jeremybennettI've just posted a link to this: http://www.eetimes.com/document.asp?doc_id=131975407:43
jeremybennettFPGA board for $2407:43
jeremybennettFPGA board for $24$2507:43
jeremybennettFPGA board for $2507:43
jeremybennett(third time lucky - fingers haven't woken up)07:44
olofkjeremybennett: I saw that one yesterday07:45
olofkIt's a nice little I/O extender for rPi07:45
olofkBut I don't think it can be considered to "offer humongous computational performance" with a little Mach XO2 as it is said in the article :)07:47
stekernit depends what you want to calculate and what you compare with ;)07:53
stekernbut yeah, 7k LUTs won't get you very far and then you have to step up to $35 to get that07:54
jeremybennettstekern: Ah - that is the magic bit of info. How many LUTs do you need for ORPSoCv3?07:55
stekernthe orpsocv3 for de0 nano we built for the workshop is 9493 LE (and an altera LE is a 4-input LUT and a flip-flop)07:59
hansfbaierHi all, are the orconf slides already online, and if yes, where?07:59
olofkhansfbaier: At least my slides are not ready yet.08:02
olofkBut I guess there will be links on orconf.org08:03
stekernMaybe we should prepare the page so people can add their slides, like on the orconf2012 page08:04
stekernmine would be ready to put up there08:04
olofkstekern: Good idea08:04
olofkI'm going to set up a placeholder repo for a unified test suite now. Is or1k-tests fine with everyone?08:04
olofkOr perhaps or1k-testsuite08:05
olofkThe internal structure can be decided later08:05
stekernI think or1k-tests is fine08:05
stekernthe question is where tests like "uart-simple" should go08:06
olofkjeremybennett: What would be the sensible thing to do with the PIF is to remove the openrisc from orpsocv3 and just add a <something-like-spi> to wb bridge that connects to the rPi08:06
olofkstekern: I've been thinking about that too. One way to see it is thatt hey really belong to the UART, as they are not OpenRISC-specific08:08
olofkBut I'm not sure that's the best approach from a usability point of view08:09
stekernwe don't have that many peripheral tests that we actually use though (that's the only one), so I'm not sure if it's really much of a real issue08:10
stekernwe could just replace it with an "hello world" test that prints via printf, and make sure it's compiled so the uart is used for that when run from orpsoc08:11
olofkYes. If we are only interested in getting characters to the screen, we should make the compiler/linker choose l.nop 4 or the uart driver depending on the target08:14
olofkAnd with my fancy uart model, we should be able to use the real uart driver without noticable slowdown in RTL simulations08:15
jeremybennetthansfbaier: stekern: I'll ask simoncook to start preparing this (he has all the videos). I have slides from several of the speakers, and we can add more as they arrive.08:18
hansfbaierjeremybennett: Thanks.08:19
juliusbah who created that unified test suite!?08:42
juliusbbravo!08:42
* juliusb cheers08:42
juliusbgithub informs me the user's name was olofk08:42
olofkOh that old repo. That was ages ago08:43
juliusbso, nice going olofk! I was going to do a similar thing last night but instead read the slides from that ohwr.org conference - Bruce Perens' video is great08:43
juliusbolofk: oh is it ready for deprecation?08:44
stekernwe that closely follow IRC knew about it 40 mins ago already ;)08:44
olofk:)08:44
stekernolofk: I'm thinking of making the testbenches for sublime (that's what I've dubbed my ongoing synth) orpsoc driven08:46
olofkstekern: That's a good idea.08:47
stekernI need to take a look at the WB transactor stuff, but can I easily use that to read/write to/from a wb-slave?08:48
olofkYes. That's the idea08:48
juliusbok, the UART tests question - I say we somehow arrange for system-specific (board-specific, in ye olde ORPSoCv2 terms) software to be included in that repo08:49
olofkThe transactor contains logic for sending a number of requests and read them back to check that they are equal08:49
juliusbas knz asked at ORCONF, is there a standard memory map for ORPSoC? I think there should be and we should write any peripheral-dependent software to use those addresses, or at least pull in a header which is generated per-system08:49
olofkInternally it uses wb_bfm_master, which probably is what you will use if you want to do something more advanced than that08:50
olofkjuliusb: We should find that document that already specifies a memory map and see if it makes any sense08:50
stekernolofk: hmm, ok... but what I want is to setup a set of wb writes to setup the registers of the core, and then read a different set of register to see status. Then I will need a wb slave that a master interface of the core will write to, and somehow verify what it writes there makes sense08:52
knzjuliusb: alternatively you could mandate the existence of a device map at a fixed address08:52
knzI do this in my own research08:52
knzsay "at this address, there will be a rom with a list of the platform's features encoded with some standard data structure"08:53
knzacpi-style, but simpler08:53
stekernbut, as I said, I should probably take a look at the things before I start ask questions08:53
olofkstekern: Yes, you can use wb_bfm_master for that08:54
stekernI just want to check that "yes, you can do that"08:54
stekerngreat, that's what I wanted to know for now08:54
olofkknz: I've been looking at sdb for that08:54
stekernI did a device-tree-blob-core for that on the atlys board08:55
knzwhat's sdb?08:55
olofkknz: http://www.ohwr.org/projects/fpga-config-space08:56
stekernhttp://en.wikipedia.org/wiki/Safe_deposit_box08:56
olofk:)08:56
knz:)08:56
stekernit's all part of olofk's enterprise edition of orpsocv3, you'll need to pay some extra license fee to get the key to unlock the device description08:58
knzhum08:59
knzI'm reading the sdb spec right now08:59
olofkstekern: I knew it was a good idea to hire you for marketing08:59
knzit feels quite over-engineerd08:59
knzthis is a tool with fpga EDA in mind, where you can reverse-engineer the FPGA design flow from the sdb data structures09:00
olofkknz: Yes. That was my opinion too when I first read it. What you are holding in your hand is actually a much simplified version09:00
knzbut to implement an OS this is wayy too complicated09:00
olofkOS=Operating System?09:00
knzyes09:00
olofkNot seeing the connection09:01
knzwhat juliusb calls "peripheral-dependent software"09:01
knzI generalize; an OS has both "peripheral-dependent software" (device drivers) and a physical memory manager which needs to know where D-RAM is mapped into the address space09:02
knzwell09:02
knzRAM, not specifically dram09:02
knzunrelated: what's the relation between opencores and the open hardware repository?09:04
stekernhmm, they are speaking about device drivers and linking them to the bus... most device drivers for the cores we use are bus agnostic09:06
knzyou can't be fully bus agnostic unless you have a fixed address map09:10
stekernof course you can, by using the standard chosen in the kernel, device tree09:12
stekernLinux specific, but the chapter I referred to was as well09:12
olofksdb was originally called sdwb as in self-describing wishbone bus09:47
olofksimbus looks really cool. Would have been great to play with at work, but all our designs are VHDL :(10:43
olofkExcept for the skunk work stuff I've been writing :)10:43
juliusbolofk: Icarus looks like it'll support (if it doens't already) the synthesisable subset of VHDL12:26
juliusbmmm, looks like Jakob just told jeremybennett exactly what he wanted to hear on the mailing lists...12:27
juliusbbut it's an interesting bug12:27
juliusbit sounds highly plausible12:28
juliusb_franck_: can you describe what it is which you think works around that bug?12:29
juliusb_franck_: oh sorry, I didn't notice you'd put a link in your email. This must also do it for the mor1kx.... hmmmm12:34
olofkjuliusb: When you say it, I remember reading that the CERN guys had put some effort into Icarus. That was probably for VHDL support. Great to hear13:10
juliusbI think they were contracting Steve Williams himself to do it (see his presentation at the ohwr conference thing)13:21
olofkI'd like to meet Steve Williams. I'm really jealous of his moustache13:27
_franck_looks like Steve Williams, the Tiger Woods' former caddie is more famous than the Icarus guy....13:30
olofk:)13:38
olofkjuliusb: What I wonder is if the bug they are seeing is in our or1200 or the FT version13:40
juliusbI suspect they've found it in theirs, and have offerred a patch based on the SVN option14:11
_franck_well if someone (other than me, because afaik it works on my platform setup) could give it a try with the latest OpenOCD...14:24
olofk_franck_: Is that the same problem that you had a patch for?14:39
_franck_I think so. However, the software workaround (write the current NPC back do the SPR flush the pipeline) should be enough14:41
_franck_s/do/to14:41
_franck_the hardware fix I did wasn't enough and I submit another one some times ago (I think it was on the ML)14:44
olofk_franck_: Hmm.. I'm getting a bit confused now. I applied a patch that you had submitted to the bug tracker and closed the bug. Should we reopen that bug, and do we want an updated hw fix, or should we go for the sw workaround?15:03
olofkLater15:09
_franck_see: http://openrisc.2316802.n4.nabble.com/OpenRISC-OR1200-RTL-fix-svn-commit-859-Execute-trapped-instruction-after-breakpoint-is-removed-td4641542.html15:13
-!- impure_hate is now known as kvapka17:34
-!- kvapka is now known as impure_hate18:17
rfajardodoes any of you understand the building system of or1k-src?19:11
stekernmultidimensional arrays in port declaration, please be supported soon!20:13
--- Log closed Sat Oct 12 00:00:36 2013

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