IRC logs for #openrisc Tuesday, 2013-09-17

--- Log opened Tue Sep 17 00:00:59 2013
stekernnice, I can read/write the FPGA DDR3 from the arm side now as well03:09
hansfbaierstekern: Did you get the Parallela?03:21
stekernhansfbaier: no, haven't got that yet04:44
stekernthis is the arrow/terasic sockit board I'm playing with04:45
hansfbaierwow that's a really good price for a FPGA like that. Is Quartus still free for that one?04:52
hansfbaierCompetitor to the Zynq as it looks04:53
hansfbaierOh it's out of stock. No wonder04:55
stekernyes, you can use the quartus web edition with it04:58
hansfbaierI almost regret ordering the parallela. but its $100 cheaper and has the epiphany. Smaller FPGA though.05:24
stekernfor me, the sockit was $100 cheaper than parallela05:33
hansfbaierstekern: academic?05:34
hansfbaier(sob sob)05:34
hansfbaierI guess I should resume college05:35
stekernlooks like arrow have them in stock, 50$ cheaper too:
stekernhansfbaier: no, I'm 10 years out of any academic work =)05:36
stekernarrow organized a workshop for $99, and the kit was given away at the workshop05:37
hansfbaierstekern: Wow great deal05:37
hansfbaierstekern: I'd like to attend workshops like that too ;)05:38
stekernit was olofk that hinted me about it05:38
hansfbaierBut I might waste multiples on airplane tickets...05:38
hansfbaierstekern: How would it be possible to interface the ARM <-> OpenRisc on the Parallela/SocKit?05:39
hansfbaierstekern: some kine of wishbone/AHB-Bridge?05:40
hansfbaierstekern: do you know of something like that?05:40
stekernyeah, I think they *did* do the workshops in asia, but the board freebie did not apply there05:40
hansfbaierAsians are too greedy05:40
stekern(interface) on the sockit, you can expose an AXI slave to the FPGA to access the ARM soc and an AXI master to access the FPGA from the ARM05:44
stekernqsys can automatically bridge the AXI bus to Avalon, which is easier to bridge to wishbone05:45
hansfbaierstekern: Ah great. Yes avalon is almost wishbone except for a couple of gates.05:46
stekernThe ARM DDR3 SDRAM is also exposed as an avalon bus to the FPGA05:46
hansfbaierstekern: nice playground for OpenRISC05:47
hansfbaierstekern: The board is awesome value for money $250 for a 110k-FPGA is really good05:47
stekernso, what I have currently working is: accessing the ARM DDR3 from orpsoc (i.e. openrisc) and accessing the FPGA DDR3 from the ARM05:47
stekernto clarify, there are two 1GB SDRAMs on the board, one for the ARM side and one for the FPGA side to use05:48
stekernnext step is to do exactly what you asked about, hook up the ARM to the orpsoc wishbone bus05:49
hansfbaierstekern: What would be a good way to make the ARM and the OpenRISC work together?05:52
hansfbaierstekern: some kind of FIFO on the Wishbone Bus?05:53
hansfbaierstekern: or shared mem, but that would need some kind of synch maybe a hardware semaphore or so05:53
stekernyeah, I think shared mem probably makes most sense05:53
hansfbaierOr run two instances on linux on ARM and OpenRISC05:54
stekernbut I guess it depends on what you want to do05:54
hansfbaierand implement a network driver that uses wishbone05:54
hansfbaierthat would be fun too05:55
stekernhmm, how do you mean? "network driver that uses wishbone"05:55
stekernright now, I'm mostly looking at the arm machine as a "tightly coupled dev machine" though =)05:56
stekernbut regarding networking, I'm planning on hooking up the ARMs second MAC to a MAC on the FPGA side05:59
hansfbaierstekern: shared mem06:04
hansfbaieras network driver?06:04
hansfbaierwould that make sense?06:05
hansfbaierjust hand over the tx/rx buffers to the other machine06:05
-!- Netsplit *.net <-> *.split quits: simoncook06:09
--- Log closed Tue Sep 17 06:21:40 2013
--- Log opened Tue Sep 17 06:21:53 2013
-!- Irssi: #openrisc: Total of 26 nicks [0 ops, 0 halfops, 0 voices, 26 normal]06:21
-!- Irssi: Join to #openrisc was synced in 24 secs06:22
stekernhansfbaier: ah, you mean like that06:36
stekernyes, that'd be pretty cool, and more lightweight than using a mac to interface another mac on-chip06:37
stekernbut, I'm lazy, so I chose to do that to utilize already existing drivers ;)06:37
hansfbaierstekern: this might be a good starting point:07:10
hansfbaierstekern: I'll try to cancel my parallela order and if it succeeds, I'll get the sockit.07:10
stekernwhy not get both ;)07:13
stekernI have an order on a parallella too07:16
hansfbaierstekern: Two reasons: 1. Having a lot of hardware lying around with no time playing with it bothers me07:44
hansfbaier2. the money07:44
hansfbaier(I have another pet project: An automated hydroponics nutritioning and watering system, ideally on solar power. That eats up considerable time and money too)07:46
hansfbaierbut will be a lot of fun07:46
hansfbaierfinally growing my own vegetables but without the work of irrigation etc.07:46
hansfbaierJust set the uC and go07:47
hansfbaierThere is no food like fresh harvested food.07:47
hansfbaierThat is a class of its own. No comparison with supermarket / organic etc.07:47
olofkstekern: I won't accept that pull request. orpsoc-cores is a drug free repo, so don't even think about pushing a diila08:01
olofkwhoops... did I remove the branch option from GithubProvider? Shouldn't matter though. A branch can be specified with the version tag as well08:02
olofkThe only problem will occur when someone gives the same name to a branch and a tag. Haven't got a clue what will happen then08:03
stekernolofk: that's bad git practice anyway ;)08:23
olofkstekern: Good to know. I was worried that it was the common way to do it08:24
stekernshouldn't it be the diila that does da pushing?08:27
stekernolofk: food for thought, would it be a bad idea to specify the "offset" in the master definition for each slave instead of under the slave definition in the .conf file for wb_intercon_gen?08:32
stekernto illustrate, something like this:
stekernthe reason I ask is that I've got a 2MB address space on a bus coming from the arm now, and I'd like to map those efficiently onto "all" the peripherals on the wishbone bus (currently it's only uart and gpio, but there will be more)08:40
stekernright now I just split up the 21-bit address to the 8-bit MSB of the wb address (to select peripheral) and use the rest to access registers withing peripherals08:41
stekernthat works, until I nead to access more than 4096 bytes within a peripheral08:42
olofkHmm.. I'm not sure I follow that. Will that mean that the address map will appear differently to the different masters?08:52
olofkPro: It can be done and would make wb_intercon more flexible08:54
olofkCon: It could be a bit messy to have different address depending on where you come from08:55
stekernagree and agree08:56
olofkIf this is an uncommon practice, I think I would prefer to have an external address shuffling block on the master that needs it08:56
stekernmmm, that's an alternative08:57
stekernI might lean towards that too08:57
olofkThat gives you the freedom to do all crazy kind of things in there :)08:57
olofkAnd wb_intercon won't have a clue that someone is lying to it08:58
stekernwell, essentially, that's what I already do, but you can of course do it more "cleverly" than just split up the address08:58
olofkDo you need 8 bit MSB to select peripheral?08:59
stekernpoor wb_intercon, if it just knew all the lies I'm telling it ;)08:59
stekernnaah, but that's the easiest08:59
olofkIt might be common enough for a wb_remap block or something like that09:00
stekernthat's the orpsocv2 way of doing it09:00
olofkCould help with the interrupt vectors too, right?09:00
stekerntrue, if it's made generic enough09:01
olofkMight need a few more use cases to see if it's worth making a generic one09:01
stekernyeah, it's a bit of a "special" case this assymetrical dual core setup09:02
stekernbut it's a whole lot more fun building socs with orpsocv3 than orpsocv2 at least09:04
stekernadding slaves and masters to the bus was such a pain in orpsocv2...09:05
olofkYeah, on the few occasions I needed an extra slave I usually just replaced an existing one :)09:16
jeremybennettJust checked ORCONF and see we are up to 20 participants now. Some well known names there, but a lot of new participants, so it will be a good opportunity to attract some new people to the project.13:11
jeremybennett(still time to register:
hansfbaierstekern: Just ordered my SocKit. Adapteva kindly canceled my order. Thanks for the tip!13:50
poke53282A news about jor1k15:28
poke53282Finally made it on the first page15:28
jeremybennettJust heard that Jon Woodruff has agreed to talk about the CHERI processor (open source MIPS clone) at ORCONF.15:47
stekernpoke53282: Congrats! and seems to be positive feedback there too, you've certainly earned that19:53
poke53282"Technical merits and uses aside, I'm still floored that this kind of thing is even possible.21:03
poke53282I've loaded it up and there's Monkey Island running on ScummVM running in a Linux VM running in Chrome's Javascript VM. Stunning." <- mjfisher21:03
poke53282I should put a direct link to opencores website. You all earned it too. I did only the last step.21:09
poke53282"Fantastic. I love that it's OpenRISC based rather than the "obvious" choice of yet another x86 emulator. And framebuffer support, though slow." <- vidarh21:18
stekernah, well, there been many before us current active openriscers, so every "last step" is an important step I'd say21:19
poke53282is there a way to see the stats of my github site?21:26
poke53282gh-pages site I mean21:27
poke53282Seems not21:30
poke53282I guess that the the whole download volume will exceed 100GB for the github page today. I am glad that I didn't put it on my website.22:38
--- Log closed Wed Sep 18 00:00:01 2013

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