IRC logs for #openrisc Monday, 2013-09-16

--- Log opened Mon Sep 16 00:00:58 2013
olofkstekern: Hey! Don't steal my catch phrases ;)06:13
olofk_franck_: That function doesn't have any return value06:17
olofkI probably should clean up the provider code and make a proper API06:17
olofk_franck_: Ahh. now I see. The idea is that it will return something if it had to download anything.06:39
olofkIt's not very pretty I see now06:40
_franck_self.fetch should return True at some point if we want self.patch to be called in core.py08:30
olofkYes, and I think it does. At least it works for OpenCoresProvider09:49
stekernlooks like mor1kx have surpassed or1200 in stability, I get nothing out of that on the sockit...11:21
stekernI'm pretty confident the wb<->avl bridge should be ok now, so wonder what might be wrong then11:22
stekernolofk: did you see my comment about wb_mux fall back earlier?11:30
olofkYes, but I thought it was something wrong with GPIO11:31
olofkBut you're correct that the fall back logic is a bit backwards since it's the first slave that is the fallback slave11:33
olofkIt's just a matter of reversign the for loop11:33
olofkAnd I plan to add watchdog timers to individual wb ports, like the one that is built-in in the orpsocv2 arbiters11:34
olofkhmm... but when I think about it now I guess it would make sense to raise wb_err when no slave matches11:37
olofkAdding a fallback dummy port that covers the whole address range just to catch errors feels a bit clunky11:39
stekernyes, it was more the "error when no match" I was thinking about11:40
stekernthe "backwards" priority ordering isn't so much of an issue11:41
stekernnot sure I follow the "fallback dummy port"...11:43
stekernisn't it enough that you change:    assign wbs_cyc_o = {num_slaves{(|match)}} & (wbm_cyc_i << slave_sel);11:56
stekernto:    assign wbs_cyc_o = match & (wbm_cyc_i << slave_sel);11:56
olofkOr even match & {num_slaves{wbm_cyc_i}} ?12:00
stekernhmm, no12:01
olofkAh no.. you're right12:01
olofkAnyway. What I meant with the fallback dummy port is that you can fake bus errors by setting a slave that covers every address and just responds with wb_err12:03
olofkBut handling it internally in wb_mux is a nicer solution.12:03
stekernyou'll still need the watchdog though, unless you don't do something like this: assign wbm_err_o = wbs_err_i[slave_sel] | !match[slave_sel] & wbm_cyc_i;12:05
olofkwb_err should just be wbm_cyc_i & !(|match), right?12:05
olofkoh.. right. Forgot about the real errors from slaves12:05
stekerna bit nasty connecting the wbm_cyc_i straight to err_i, but not sure if you (easily) can avoid it12:06
olofkYes. Watchdogs will be necessary if a core has locked up, but handling known invalid addresses is another problem12:07
stekernor.. would be easy to just register the  !match[slave_sel] & wbm_cyc_i of course...12:07
olofknasty why? I could register it if you worry about the timing12:07
stekernyou'll (potentially, depends on the master) get a combloop between cyc and err12:08
olofkso final solution : assign wbm_err_o = wbs_err_i[slave_sel] | (wbm_cyc_i & !(|match))12:08
olofkWith a register of course12:08
stekernsounds right12:09
stekernI think the 'OR' you proposed is better than using the select too12:09
stekernshould be more lightweitgh than going through the priority decoder12:10
olofkI'll add that to the ORPSoC EE Critical Failsafe support package12:10
stekernI assume I'll need a seperate floppy-disk dongle for that?12:11
olofkI should run this through synthesis and check the RTL. I think it could be a mess right now12:11
olofkYou _do_ have two floppy controllers in your computer, right? Otherwise you will only be able to unlock one feature at a time12:12
stekernI must say it's a genius move to use the floppy-disk instead of usb dongles, everybody are short of usb ports, but the floppy disk drives are just there unused!12:13
stekernah, but I don't mind floppy juggling, reminds me of the good old times12:13
olofkI should run wb_mux and wb_arbiter through synthesis and check the RTL. I think it could be a mess right now with all the decoding and encoding of select signals12:35
stekern I haven't looked very closely, but it didn't look too bad.. I think12:36
stekernfound the problem with or1200, I had typos in the data bus signals13:45
knzhi guyes14:15
knzwhat's the value of EM_OR1K in the elf headers?14:15
knzI'm not sure how to find it in binary files14:15
knzoh never mind found it14:15
knzother question: is the or1k implementation little endian by default?14:23
stekernknz: it's big endian by default, and that's currently the only endian supported15:27
stekern_franck_: I can't pull with that commit specified, you still have stuff before that I don't want15:31
stekernI cherry-picked it in from my tree now15:34
knzstekern: thanks16:12
crbowmanI'm trying to synthesize with DC, I've TCLized the synthesis script but when I try to link or compile I get "unable to resolve reference" for a bunch of top level modules16:54
crbowmanIt seems to be related to parameterization. For instance or1200_wb_biu is being instantiated twice with parameter 4 which happens to be the default for that parameter value.16:54
crbowmanWhen the parameter value is overridden via the instantiation I get unresolved references, when I remove the override and let the default get used (which is the same value) then or1200_wb_biu is not unresolved.  Has anyone seen this issue?16:54
olofkcrbowman: I haven't used DC with or1200, but I haven't seen problems like this with any other tool16:59
olofkCould it be some problems with your setup?16:59
olofkDo you have or1200-defines.v as an include file for example17:00
crbowmanIt could absolutely, but I'm not a DC expert so I don't have a clue what it could be, I translated the existing DC script to TCL pretty directly as far as I know.  Someone else here took a look and they could see it either17:00
crbowmanI haven't touched the source at all and convert the set or read in files verbatim in the TCL script17:01
stekernyay! Linux booted on mor1kx@sockit now!17:04
olofkstekern: Congratulations. If it's orpsocv3-based it's a great success for me too :)17:05
stekernof course it is orpsocv3-based!17:05
olofkyay! GNU/Linux booted on orpsocv3/mor1kx@sockit now!17:07
stekernI've got or1200 booting Linux too17:07
olofkOr busybox is perhaps not GNU?17:08
stekernrunning minicom in gtkterm doesn't work well btw17:09
stekernssh:ing in to the arm machine and running minicom there does17:10
olofkHow much stuff are you running on the ARM?17:12
stekerndefine "running"17:12
stekernI've got the default Linux image loaded to the sdcard17:12
stekernand an updated u-boot-spl written into that partition, to get the uart exposed to the FPGA17:13
stekerneverything else is vanilla so far17:14
stekernand right now the hps is cold-reset from wb_rst, so it's annoyingly rebooting all the time :/17:15
stekernbut I had to do that, because otherwise it locks up when I connect openocd to adv_debug_if17:15
stekernnext is to get some more control over mor1kx from the arm, like asserting resets and loading stuff into memory for it to run17:16
olofkThat sounds like fun17:17
stekernreally cool would be if I could get debugging working from the arm17:17
stekernI mean, running a debug bridge and gdb on the arm machine17:17
stekernnot sure how easily you can compile openocd for it17:18
olofkI thought about that too17:19
crbowmanIt's really odd because if I take one of the module and use the default parameters without over ride it works, but leaving in the override get me unresolved issues17:22
stekernI have to hook up ethernet from orpsocv3/mor1kx to the second mac of the hps too17:22
stekerncrbowman: what "existing" DC script are you talking about?17:23
stekernheh, I never noticed those...17:26
stekernwonder how ancient they are?17:26
olofkNever seen them either17:27
stekern1575d 09hunneback17:28
stekernand that's just import from other repo17:28
olofkunneback is probably Michael Unneb├Ąck, but it might just be that he did the CVS->SVN conversion17:29
--- Log closed Tue Sep 17 00:00:59 2013

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