IRC logs for #openrisc Wednesday, 2013-09-18

--- Log opened Wed Sep 18 00:00:01 2013
stekernaccessing wishbone peripherals from the arm works now02:59
stekernolofk: I updated the pull request to include the avalon to wishbone bridge as weel03:00
stekernI should make some testbenches for those, but the altera BFMs are some encrypted crap that only works in modelsim...03:01
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hansfbaierstekern: Do you have any idea what to do with the HSMC connector on the SocKit board? It seems to be pretty hard to find anything useful on google/ebay/aliexpress06:13
stekernhansfbaier: don't know, I would probably buy something like this:
hansfbaierstekern: ah thanks07:11
hansfbaierstekern: wow this cable is more expensive than the board. Crazy!07:12
stekernthis is cheaper
olofkpoke53283: (ycombinator) Ahh.. so that's why there was a torrent of tweets about jor1k today. Nice to see. Congratulations and good work07:20
-!- Netsplit *.net <-> *.split quits: hno, knz07:42
-!- Netsplit over, joins: hno07:43
-!- Netsplit over, joins: knz07:43
olofkstekern: Pull request closed now09:34
stekernI'm able to load a binary into the FPGA DDR3 from ARM u-boot now, and then toggle the wb/or1k reset line so it start executing from that now10:10
stekernI can toggle the reset line with "normal" linux tools too, so I've loaded the ram in u-boot, booted arm linux, run minicom and toggle reset line => "Hello world!"10:11
olofkhaha. That's awesome10:15
stekernhave to make that a bit more userfriendly though ;)10:16
stekernI have to manually fiddle with the arms hps2fpga bridge reset lines in u-boot to enable that first too10:16
stekernI had to add an wishbone interface to clkgen to get this working10:18
stekernwhich is nice, then I can make some clock programmable from wishbone too ;)10:19
stekernpixel clock comes to mind...10:19
olofkThat's a good idea10:29
olofkwb_intercon_gen is becoming a bit messy now with the wb_data_resize support12:15
stekernolofk: you are adding that?12:17
olofkYep. You sound surprised?12:24
stekernheh, no, not all13:23
stekernI was just curious13:27
stekerndid you push wb_intercon_gen btw?13:27
stekernI should update my interface to it in sockit13:28
stekernbut I want to have the component and wires autogenerated before I do that, so I could help out doing that if you don't have an urge to do it yourself13:29
stekernit's no big hurry though13:29
stekernI'm thinking we could just `include the autogenerated file in top13:30
olofk`include-ing it is a great idea. Haven't even thought about that13:32
olofkYou're welcome to add the instantiation template. I will have my hands full with the wb_data_resize stuff13:33
olofkI'm contemplating a rewrite of wb_intercon_gen actually, but I'm not sure it's worth it13:33
olofkActually, I think it's worth it. Especially if we want to add CDC fifos13:42
stekernI'll try to make the template code not to tied in then14:23
stekernmight be beneficial elsewhere too14:24
stekernat first sight, I think most will be done in verilogwriter anyway14:25
poke53281olofk: Thanks. Do you have a link? I am complete noob using twitter.16:33
olofkpoke53281: I have twitter searches triggered for tweets that contain openrisc or opencores, so that's how I saw them, but you should probably just be able to got to and search for openrisc or jor1k17:06
olofkstekern: Yeah. It's probably a good idea to put it in verilog_writer.17:08
poke53281Hehe, saw your twitter olofk19:37
poke53281You know Adam Dunkels?19:42
olofkpoke53281: I don't know him personally, but I've been following some of his work21:05
poke53281I tried his contiki operating system on the C64 emulator with network support.21:35
poke53281Amazing that I could surf my favorite news sites with that system.21:35
poke5328164kB RAM, 8 Bit Data, 16 Bit Address Bus, 1MHz21:36
poke53281This is already 10 years ago.21:40
--- Log closed Thu Sep 19 00:00:02 2013

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