| --- Log opened Fri Aug 09 00:00:03 2013 | ||
| stekern | olofk: hilfe: http://pastie.org/8220583 | 03:21 |
|---|---|---|
| juliusb | olofk: great choice with the no-SystemC thing with verilator. It's a pain to install those things it needs (Verlog-Perl, System-Perl and then the System C kernel stuff) | 09:54 |
| juliusb | olofk: yuo can get Icarus to generate traces in LXT2 or something, that's binary and far more compressed than VCD AFAIK | 09:55 |
| juliusb | stekern: I added a feature to or1ksim which allows you send a signal to it to trigger instruction trace generation, maybe we could do that for the RTL model stuff.... or perhaps somewhere where we connect GDB to the model, run it to a suspected problem area, then do some sort of memory access which will cause triggering to begin and then unstall the processor and let it do its buggy business | 09:57 |
| juliusb | (BTW LXT in verilator can be achieved with this wonderful piece of hackery: http://www.veripool.org/boards/2/topics/150-Verilator-Converting-VCD-file-to-LXT-file-during-simulation ) | 10:04 |
| stekern | juliusb: yeah, that kind of thing would be useful | 10:48 |
| stekern | but really, the vcd backlog is what I'd really want | 10:50 |
| stekern | because most often, you are interested in what happened before a trigger | 10:51 |
| stekern | right now, I'd really like ISE to support verilog dot notion... | 11:01 |
| stekern | why isn't that supported in the synthesis tools? | 11:01 |
| stekern | I'm almost inclined to write some parser to bring signals out to the top level | 11:29 |
| stekern | because doing it by hand is too boring | 11:29 |
| juliusb | stekern: that's a _very_ good question | 13:39 |
| juliusb | and in fact, we have a tool which we use all the time internally which does that | 13:40 |
| juliusb | for FPGA builds, anyway | 13:40 |
| juliusb | it's very simple to do | 13:40 |
| juliusb | it should just be in the spec, that it's allowed | 13:40 |
| stekern | it's actually not _that_ bad to do it by hand with the autoargs | 14:48 |
| stekern | I just want to kill this bug that makes gcc go boom | 15:01 |
| stekern | another thing that'd be cool, would be to add ata emulation to the verilator model | 15:10 |
| juliusb | yes, what for? | 18:49 |
| juliusb | can you hook it up to a linux device then or something and get actual disk accesses? | 19:09 |
| --- Log closed Sat Aug 10 00:00:05 2013 | ||
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