| --- Log opened Thu Aug 08 00:00:02 2013 | ||
| stekern | olofk: ok, but what does the tools do? i.e. how does it work | 09:53 |
|---|---|---|
| stekern | say I have my rtl in there, what is it that orpsocv3 do? and how do I make it do that? | 09:54 |
| stekern | and is the 'generic' and 'generic-or1200' usable? and what's the difference between the two? | 09:55 |
| stekern | say I want to run a simulation with the generic 'system', how do I do that? | 09:55 |
| * ams ponders. | 10:46 | |
| olofk | stekern: Both systems should be usable. Try orpsoc sim or1200-generic --or1k-elf-load=<path to elf file with test case> | 11:43 |
| olofk | generic is made to mimic the reference system from orpsocv2, and should be synthesisable | 11:45 |
| olofk | or1200-generic is a minimal system that is mainly for testing or1200 itself | 11:46 |
| arokux1 | hi stekern | 11:47 |
| arokux1 | stekern, are there any todos for orpsocv3? | 11:48 |
| olofk | arokux1: I'm the one who's doing orpsocv3, and yes, there are lots of todos :) | 11:48 |
| arokux1 | olofk, is there a list of them? | 11:51 |
| olofk | arokux1: Yes, but it's a bit incomplete and not very up to date. You can find it in the orpsoc repo at git.opencores.org | 11:52 |
| arokux1 | olofk, ok! | 11:53 |
| olofk | I'm currently working on verilator support and some helper functions to easier create wishbne interconnect blocks | 11:54 |
| arokux1 | ok, i'd need to learn a lot of things before I can do smth, I was asking for an entrance point. | 11:55 |
| olofk | Entrance point for doing OpenRISC stuff in general? | 11:56 |
| arokux1 | olofk, for doing hardware design, at the high level for the start i.e. assembling boards | 11:57 |
| olofk | I'm not very good at those things, unfortunately | 12:00 |
| arokux1 | olofk, what are you doing then? | 12:01 |
| olofk | Creating a framework for connecting cores, running simulations and create FPGA images. | 12:04 |
| olofk | I haven't done any PCB design at all | 12:05 |
| arokux1 | ah wait, soc is only a part of a board | 12:05 |
| arokux1 | do you also do board assembly in the project? | 12:06 |
| olofk | No, I only generate the contents of the FPGA. Maybe you should talk to the guys at dangerous prototypes. The do a lot more board designs | 12:07 |
| olofk | They seem to have a very active community for it too | 12:08 |
| arokux1 | ok | 12:08 |
| arokux1 | thank you olofk | 12:08 |
| arokux1 | btw, do you know about upverters? | 12:08 |
| olofk | I guess it's the opposite of a downverter :) | 12:09 |
| arokux1 | olofk, no, has nothing to do with it :) | 12:09 |
| olofk | Is it something like the "Ham it up"? | 12:10 |
| olofk | I might be the wrong guy to ask here. Only wild guesses | 12:10 |
| arokux1 | olofk, https://upverter.com/ no, it's like github only for hardware projects | 12:12 |
| olofk | aha. That's cool. Should check it out for some ideas | 12:12 |
| olofk | What we are doing here falls a bit inbetween software and hardware, so we struggle a bit with our identity and don't feel welcome anywhere | 12:15 |
| olofk | In fact, we are so linely that we had to create our own conference...only for us | 12:15 |
| olofk | s/linely/lonely | 12:15 |
| olofk | But at least we have our own cheerleader group. Go SoC Kittens! | 12:23 |
| arokux1 | I see olofk | 12:24 |
| arokux1 | olofk, the problem for you is that you cannot produce (real) prototypes and are force to do it in FPGA, that is why it is between software and hardware? | 12:55 |
| stekern | no, the problem is that rtl design is a gray zone between hardware and software design | 12:57 |
| stekern | at least in the open source world | 12:57 |
| hno | arokux1, what is "real" prototypes? | 12:58 |
| arokux1 | hno, chips in silicon, not fpga, anyway it was just a thought. | 12:59 |
| hno | arokux1, making silicon is very late in the process. There is silocon versions of OpenRISC even (Allwinner A31 have one) | 13:01 |
| arokux1 | hno, ok | 13:05 |
| stekern | and FPGA is not (necessary) equal to prototyping | 13:07 |
| olofk | Great. Got a verilated model now. Time to raid orpsocv2 again for some test bench glue logic | 13:10 |
| olofk | I chose to go with pure c++ output from verilator to avoid a dependency on systemc. Any downsides to that? | 13:11 |
| stekern | no idea | 13:16 |
| stekern | thanks for the hand holding btw | 13:16 |
| stekern | I like the debug flow I have with verilator, right now I'm debugging a problem that only shows itself when I run gcc with hw tlb reload enabled | 13:17 |
| stekern | pretty hard to pin down in both simulations and hw | 13:18 |
| stekern | so what I do instead is to add a bit of $displays with possible corner cases, run things in verilator to get the $time when it happens | 13:19 |
| stekern | then rerun with vcd generation on around that $time | 13:20 |
| olofk | stekern: It's good to know what kind of features that people are looking for. Both verilator support and delayed VCD generation is on my todo list | 14:00 |
| olofk | I also plan to add sqlite support to or1200-monitor (and mor1kx-monitor) so I can analyze large instruction traces more efficiently | 14:01 |
| olofk | My linux boot experiment in icarus was a pain since I got several GB of clear text log files to look at | 14:02 |
| stekern | delayed VCD generation, but what also would be nice would be triggered VCD and trace generation | 14:16 |
| stekern | and (if at all possible) vcd ring buffer is a feature I'd like | 14:17 |
| stekern | i.e. to have a fixed (say 500MB) size vcd backlog | 14:18 |
| stekern | I don't mind the clear text trace logs | 14:19 |
| stekern | I wouldn't care using compressed/sqlite trace logs | 14:19 |
| stekern | better to selectively generate the text logs then | 14:19 |
| stekern | I pretty often direct the output to a named pipe and then tail -f that | 14:22 |
| stekern | or grep it for something I'm interested in | 14:22 |
| --- Log closed Fri Aug 09 00:00:03 2013 | ||
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