IRC logs for #openrisc Sunday, 2013-04-28

--- Log opened Sun Apr 28 00:00:34 2013
stekernjuliusb: so like a prefetcher?02:20
stekernfew-word caches is basically what I have in the SDRAM controller, one for each port, to hold a 1 burst length02:25
stekern(or was it 2 bursts perhaps)02:28
stekernanyways, from the testing I did when I wrote that, you get a really good speed up with a small cache like that alone02:29
stekernbut otoh, if you now connect pronto to my sdram controller, you'll not notice much of a difference, since the few-word cache already is there02:30
stekernjuliusb: I just tested running the kernel without the latched-level irq workaround, works fine02:59
@juliusbstekern: (interrupts) nice, which did you use - edge or level?10:20
@juliusbor do both work?10:20
@juliusbas you've said before, these fetchers are not friendly are they? you have to spend a lot of time with them to talk them around to seeing things your way11:09
@juliusbone thing which has come to mind in all of this is whether a big monolithic state machine is what I want to do in future, instead of seemingly disparate state variables11:11
@juliusbwould probably make it easier to debug and develop in future11:11
@juliusbbecause you have to remember what each signal means and is supposed to do when another signal does something11:11
@juliusband when it's in a big state machine, it's a bit more obvious11:12
stekernyou have to be a fetch whisperer to tame them, yes11:14
stekernbig state machines have their annoyances too, I tried to do that in the fetcher for a while too, but that bit me in the back end too11:15
@juliusbhmm, OK, having not done it I haven't had that experience11:16
stekernbut the cappuccino fetcher is pretty non-statesy now11:23
stekernall external (non-cache-refill) bus-accesses have one cycle latency, where it is decided if the bus access is really allowed to start11:24
stekernand then the result is registered, thus saved if fetch happen to be stalled during the bus access11:25
stekern... I still have a small statemachine in the fetcher, but that's just me having an unnatural attraction to statemachines11:26
@juliusbdon't worry, I think it's natural to be attracted to state machines with HDL design11:32
@juliusbbut doing something like this mini cache guy in pronto has brought out a few bugs in the pipeline control logic11:34
@juliusbwhich would probably have been found if it was hooked up to a slightly different bus11:34
--- Log closed Mon Apr 29 00:00:36 2013

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