| --- Log opened Sat Apr 27 00:00:33 2013 | ||
| olofk | I haven't quite figured out wishbone b3 burst accesses yet. Is the slave supposed to ignore wb_adr_i after it has registered the first access, and only check if it's a linear or incremental burst? | 14:04 |
|---|---|---|
| stekern | mnja, usually it use that address to calculate the next address | 14:24 |
| stekern | the adress that is presented on the bus is always valid for that cycle | 14:26 |
| stekern | the only difference is that the master is telling the slave what the next address will be | 14:26 |
| stekern | another kubuntu update with massive headaches... | 14:34 |
| stekern | I'm really tempted to through out that crap now | 14:34 |
| * hno is a happy Fedora user. | 15:14 | |
| stekern | yeah, that's probably what I'd swap to | 15:26 |
| @juliusb | OK some of the guides I did for chiphack rearranged and placed on the mor1kx-dev-env wiki: https://github.com/juliusbaxter/mor1kx-dev-env/wiki | 15:58 |
| @juliusb | boring but useful work over :) | 16:01 |
| @juliusb | stekern: I was asking someone after chiphack about the git pull thing I always do wrong | 16:06 |
| @juliusb | he pointed me to this | 16:06 |
| @juliusb | https://coderwall.com/p/7aymfa | 16:06 |
| @juliusb | i shall never forget :) | 16:07 |
| stekern | good, I guess I'm not as good explainer as the guy on that page ;) | 17:33 |
| @juliusb | no you are, it just takes a few times to sink in :-/ | 17:39 |
| hno | stekern, it does not barf on vga_lcd if I build for the de0 nano board, only if I build for ordb2a. Must be some different quartus settings in the two boards. | 19:39 |
| stekern | hno: ok, then it at least makes sense | 19:40 |
| hno | maybe from 'set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005' in the ordb2a tree.. | 19:45 |
| * hno guesses blindly | 19:45 | |
| hno | Seems to be it. Wonder what the default is.. but I think the vga_lcd module should be modified regardless. | 19:53 |
| stekern | default is verilog2001 | 19:57 |
| stekern | why does the ordb2a set it to that? there shouldn't be any systemverilog specific code in orpsocv2 | 19:58 |
| hno | I do not know. | 20:00 |
| hno | the setting have been there "forever" since the board port was started. | 20:02 |
| hno | stekern, this seems to do the trick: http://paste.fedoraproject.org/8921/36709322 | 20:09 |
| hno | the LWS change is unrelated obviously, needed by current orpsoc. | 20:13 |
| hno | I wonder... did I get the MOR1KX plugged in correctly on the first try? | 20:23 |
| hno | Hmm.. quartus finished but or_debug_proxy is not very happy "Error 1 occured when reading CPU NPC" | 20:29 |
| hno | so something missing/wrong I guess. | 20:36 |
| stekern | hows the debug setup on that board? | 20:55 |
| hno | There is an integrated FT4232H, with two JTAG channels (one for FPGA, one for CPU) and two UART channels. | 21:08 |
| hno | but not USB blaster compatible. | 21:11 |
| hno | stekern^ | 21:14 |
| hno | or_debug_proxy do find the debug unit and CPU type, but I guess it then fails to access the CPU. | 21:15 |
| @juliusb | hno: LoneTech would be your man on all things ordb2 | 21:15 |
| hno | I know. | 21:16 |
| @juliusb | stekern: as usual I'm working on things which are strictly not critical for mor1kx but fun | 21:16 |
| @juliusb | tonight it's a small few-word cache in the pronto fetch stage | 21:17 |
| @juliusb | just in flops | 21:17 |
| @juliusb | it might turn into a full-on cache | 21:17 |
| hno | but I don't think LoneTech have run a mor1kx on ordb2a yet. | 21:20 |
| @juliusb | ah, probably not | 21:20 |
| @juliusb | you never know, though | 21:20 |
| hno | Hm.. I wonder... lets try one thing. | 21:24 |
| hno | no. that was an or1200 only thing. remembered wrong. | 21:26 |
| hno | have a hack to work around an or1200 bus access bug, and tought that hack was in orpsoc_top, but it's in or1200_top. | 21:27 |
| --- Log closed Sun Apr 28 00:00:34 2013 | ||
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