IRC logs for #openrisc Saturday, 2013-04-27

--- Log opened Sat Apr 27 00:00:33 2013
olofkI haven't quite figured out wishbone b3 burst accesses yet. Is the slave supposed to ignore wb_adr_i after it has registered the first access, and only check if it's a linear or incremental burst?14:04
stekernmnja, usually it use that address to calculate the next address14:24
stekernthe adress that is presented on the bus is always valid for that cycle14:26
stekernthe only difference is that the master is telling the slave what the next address will be14:26
stekernanother kubuntu update with massive headaches...14:34
stekernI'm really tempted to through out that crap now14:34
* hno is a happy Fedora user.15:14
stekernyeah, that's probably what I'd swap to15:26
@juliusbOK some of the guides I did for chiphack rearranged and placed on the mor1kx-dev-env wiki:
@juliusbboring but useful work over :)16:01
@juliusbstekern: I was asking someone after chiphack about the git pull thing I always do wrong16:06
@juliusbhe pointed me to this16:06
@juliusbi shall never forget :)16:07
stekerngood, I guess I'm not as good explainer as the guy on that page ;)17:33
@juliusbno you are, it just takes a few times to sink in :-/17:39
hnostekern, it does not barf on vga_lcd if I build for the de0 nano board, only if I build for ordb2a. Must be some different quartus settings in the two boards.19:39
stekernhno: ok, then it at least makes sense19:40
hnomaybe from 'set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005' in the ordb2a tree..19:45
* hno guesses blindly19:45
hnoSeems to be it. Wonder what the default is.. but I think the vga_lcd module should be modified regardless.19:53
stekerndefault is verilog200119:57
stekernwhy does the ordb2a set it to that? there shouldn't be any systemverilog specific code in orpsocv219:58
hnoI do not know.20:00
hnothe setting have been there "forever" since the board port was started.20:02
hnostekern, this seems to do the trick:
hnothe LWS change is unrelated obviously, needed by current orpsoc.20:13
hnoI wonder... did I get the MOR1KX plugged in correctly on the first try?20:23
hnoHmm.. quartus finished but or_debug_proxy is not very happy "Error 1 occured when reading CPU NPC"20:29
hnoso something missing/wrong I guess.20:36
stekernhows the debug setup on that board?20:55
hnoThere is an integrated FT4232H, with two JTAG channels (one for FPGA, one for CPU) and two UART channels.21:08
hnobut not USB blaster compatible.21:11
hnoor_debug_proxy do find the debug unit and CPU type, but I guess it then fails to access the CPU.21:15
@juliusbhno: LoneTech would be your man on all things ordb221:15
hnoI know.21:16
@juliusbstekern: as usual I'm working on things which are strictly not critical for mor1kx but fun21:16
@juliusbtonight it's a small few-word cache in the pronto fetch stage21:17
@juliusbjust in flops21:17
@juliusbit might turn into a full-on cache21:17
hnobut I don't think LoneTech have run a mor1kx on ordb2a yet.21:20
@juliusbah, probably not21:20
@juliusbyou never know, though21:20
hnoHm.. I wonder... lets try one thing.21:24
hnono. that was an or1200 only thing. remembered wrong.21:26
hnohave a hack to work around an or1200 bus access bug, and tought that hack was in orpsoc_top, but it's in or1200_top.21:27
--- Log closed Sun Apr 28 00:00:34 2013

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