IRC logs for #openrisc Monday, 2013-03-25

--- Log opened Mon Mar 25 00:00:41 2013
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mor1kx[mor1kx] juliusbaxter pushed 2 new commits to master:
mor1kxmor1kx/master 2208039 Julius Baxter: pronto: add new "TCM" fetch unit...00:09
mor1kxmor1kx/master 46ed820 Julius Baxter: Merge branch 'master' of into debug-dev00:09
--- Log closed Mon Mar 25 01:27:12 2013
--- Log opened Mon Mar 25 01:27:59 2013
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--- Log opened Mon Mar 25 02:41:53 2013
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stekernasm: you don't, you have to hookup a ttl-uart (e.g. to the pinheader03:13
stekernand asm, I'm with you, I'm neither very interested in building ASICs for now ;)03:25
glowplug`It's not for everyone.  But at least we should aknowledge the limitations of FPGA's.  And their strengths (a development platform for IP).  8)03:34
stekernyes, no doubt about that03:36
glowplug`One thing I want to apologize for asm.  I watched a few talks on mruby (mostly rubycon 2012).  Apparently it probably WILL run on an OR1200 core.  But very very slowly.  To get your interactive ruby shell you need to first get an RTOS running on the FPGA.  The guys here can help you with that.  =)03:37
stekernthere's a 3) that you forgot in your list of "FPGAs are only good for".03:39
glowplug`Low volume highly parallel embedded tasks?03:39
stekern3) systems that need to have the same hardware, but should be sold for different purposes03:39
glowplug`Ahh.  Yes that I agree with also.  =)03:40
glowplug`FPGA's kick extreme ass at software defined radio and motion control.  ASIC's could replace them (and be cheaper and faster) but for some reason they haven't yet.  It could be an issue of sales volume.03:41
stekerntbh, i've seen a tendency to move away from ASICs towards fpgas in some application fields03:46
glowplug`Thats the world we live in.  Where ASICs are for rich people / large business's only.03:47
stekernoh, this is multibillion large businesses03:47
glowplug`The only physical way to get certain functionality is with FPGAs.  Certainly the only realistic way to test rapidly changing hardware designs.03:47
stekernbut application falls into your 2)03:48
glowplug`My only point is that they are an intermediary step.  We started with zero ability for a hobbyist to design hardware.  Now FPGA's give us a slow, expensive, but functional way to do so.  And they will eventually be enveloped by rapidly prototyped ASIC's.03:49
stekernand my point is that both have a place and purpose, our problem now is that we only can serve the needs that FPGA's serves, since we have no ability to (easily) produce ASICs03:53
glowplug`I agree completely.  =)03:54
glowplug`I think asm was looking to FPGA's for a fast efficient replacement for ASICs.  A role they can never fullfill.  Unfortunately.03:55
glowplug`Here is something you might be interested in.
glowplug`It allows you to write hardware in Python and compile to Verilog.  O_O03:58
stekernI know about it very well04:00
glowplug`Awesome!  So you have tried it?04:01
stekernhere is another:
stekernno, haven't tried it04:02
glowplug`This migen project looks very interesting.  They use it for SDR.  Thanks for the link!04:03
glowplug`I read some reports that MyHDL can sometimes general such good RTL that people at their work cannot even tell it was generated.04:04
glowplug`*sometimes generate04:04
glowplug`I'm reading through the migen documentation right now.  It seems like it is quite a bit better than MyHDL.  Very cool.04:48
stekernthey have a bit of different goals and strategies04:53
glowplug`I really like the Migen approach.  The Python side of it is much cleaner and it seems like there is a lot less room for error on the part of the coder.  Which is always good.  =)04:56
glowplug`I'm going to try and do the "blinking LED" and get the output on GTKWave.04:56
glowplug`Then start working on adding SIMD to mor1kx!04:57
glowplug`What is your opinion of the LatticeMico32 CPU?  Is it worth studying?05:10
stekernglowplug`: the architecture is very similiar to or1k06:03
stekernit's IMO less interesting since it's the child of a large semiconductor company in contrast to the completely community driven openrisc06:05
stekernthe implementation is very good from what I've seen, one of mor1kx goals is to become as good and then beat it06:06
stekern(or at least one of my goals with mor1kx-cappuccino)06:07
stekernjuliusb: what does 'TCM' stand for?06:24
stekern'git pull -r openrisc_github master' and 'git push openrisc_github debug-dev:master' are the magical commands you should remember ;)06:27
stekernor your debug-dev tree into master and then push to openrisc_github master, that way the merge message makes a lot more sense06:33
stekern*or merge your06:33
asmsweet, I finally got uclinux running06:38
asmCPU:            NIOS206:38
asmMMU:            none06:38
asmFPU:            none06:38
asmClocking:       100.0MHz06:38
asmBogoMips:       48.9406:38
asmCalibration:    24473600 loops06:38
asmsorry I went with nios206:38
stekernoh no!06:38
asmI couldn't get the orpsoc stuff working06:38
asmsoon :)06:39
stekernorpsoc for de0-nano is easy, just 'make all' and 'make pgm' and you're done with it06:40
asmyeah, well, there is one issue06:40
asmI'm running linux in a vmware vm06:40
asmand the usb passthrough doesn't seem to be working well atm06:40
asmbut I've had all kinds of usb issues today06:40
asm(had to buy a new hub)06:40
asmI'll get it ironed out eventually06:40
stekernin the boards/altera/de0_nano/syn/quartus/run/ directory06:41
asmyeah, I found the readme for the de2-11506:41
stekernah, ok, so it wasn't an orpsoc issue at all ;)06:41
asmbut I just wanted to get something working before I crash for the night06:41
stekernyeah, I understand06:41
stekernactually, I think you could build orpsoc for de0-nano under windows06:42
stekernnever tried hthough06:42
asmyup, you can06:42
asmjust kinda weird06:42
stekernas long as you have make and the altera tools in your path, you should be all set06:42
asmand I think the jtag bridge works in cygwin06:43
asmok, crash time06:43
asmthanks for all your help :)06:43
asm(and debate)06:43
stekerngood night06:43
asmtomorrow I'll get mruby loaded up on here06:43
asmnow I just have to dream of something to do with mruby that involves circuit design :)06:44
stekernI think you could get openocd compiled to run under windows too06:44
* stekern thinking out loud06:45
stekernjuliusb: pull request ohoy!07:01
stekernjeremybennett: seems like all verilator questions I google I end up on the veripool boards where you are asking exact the same questions ;)08:16
jeremybennettstekern: Which particular question?08:19
jeremybennettOne of the reasons I have a high profile is because Embecosm is paid to support Verilator.08:19
stekernoh, several, this was the latest:
olofkstekern, jeremybennett: Have you discussed about merging the frame buffer support into or1ksim? I rediscovered it a while back, and it looks like it would apply as a clean patch08:23
olofkand I like frame buffers. I think they are pretty08:23
stekernme too08:23
olofkMy unicorns and rainbows look like shit in ASCII08:23
jeremybennettstekern: Ah yes - I've done a lot of work on that, and it is not easy. Essentially Verilator follows true synthesis semantics - what you get is what you get with DC. However most simulators follow the simulation semantics. Turns out it's not so easy to add to Verilator after all. For now I've given up on it.08:24
stekernI think I pointed jeremybennett to it right after I'd done it, but I don't think he ever got around to take a look at it08:24
jeremybennettolofk: Which patch is this - I'm a bit behind.08:24
stekernwe didn't have as good patch submission routines back then08:24
jeremybennettIf Or1ksim still passes regression, and the change is documented a) in the ChangeLog and b) in the User Guide, please apply it.08:25
stekernand then I've kind of have forgot about it08:25
jeremybennettOr else send me the patch again to review.08:25
stekernolofk: if you feel like polishing it off and apply it ontop current or1ksim, that'd be cool08:26
olofkjeremybennett: Just to clarify, it was never sent as a patch, but I remembered a while back that stekern implemented it in his tree08:26
olofkstekern: Sure thing. I've been meaning to ask you if I should do that.08:27
stekern"while back" == around februari 2010 ;)08:27
olofkWhen everyone else is busy running around and implementing new stuff, I find myself digging up old patches and replying to three-year old bugs :)08:28
olofkThat's probably because I'm not in a position where I can do real coding at work08:28
stekernthat's what everybody really *should* do08:28
olofkYeah, every project needs that, and I don't mind08:28
jeremybennettolofk: stekern: We ought to follow the procedure. If you post the patch, then as maintainer I can approve it, and you can apply it.08:36
stekernyeah, sure, that sounds perfect08:36
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stekernjuliusb: I just pushed a set of patches that makes cappuccino sweep through the judgemental eyes of verilator (github announcements seems broken atm).08:52
stekernbut your TCM pipeline added a new warning:
stekernpipelining_adr is not declared and not used anywhere else than where it is defined, so I didn't want to touch it myself, since you might want to use it later or just remove it08:56
stekernjust so you know :)08:56
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stekernthe running against gcc regression suite is way cool11:07
stekernlooks like it's exposes some bug in cappuccino too11:08
stekernI found a bug in the Makefile though, it restarts from the next test after GCC_C_TESTS_START instead of that test11:27
stekernI snuck in a patch for that in the pending pull request11:28
stekernah, maybe they are not failing, but just takes very long time to finish12:02
stekernyep, it was just that, cappuccino passed all tests with flying colors12:56
juliusbstekern: TCM - tighly coupled memory, maybe a ROM or something13:00
juliusbI also haev fixes to those lint errors in verilator13:00
juliusbI have another patch to push which makes it pass all tests13:00
juliusband yes I should have done the nicer git pull command to remove the additional weird pull committ hing13:00
juliusb(btw keeping up with IRC as a web page is so much nicer than scrolling back in irssi)13:01
juliusb(so beenk eeping up with what's being said13:01
juliusbyour pull request for the verilator fixes sounds good, too13:02
juliusbsome of the GCC tests take aaages to finish13:02
juliusball up I get about 2hours of runtime when running the tests against the espressos13:03
juliusbthat's on my core i5 machine13:03
juliusb(against the verilator model, of course)13:03
juliusba nicer thing for the gcc regression stuff would be something which logged the results13:04
juliusbproceeded on failure13:04
juliusband continued13:04
juliusbanother thing I'd like is to have the start sequence program the tick timer to fire at regular intervals during all of those tests13:04
juliusbthat'd be easy to do I guess13:04
juliusbit's probably something we could have in the crt for all c-based tests13:05
stekernyeah, I figured out the TCM TLA, but this was the first hit on google:
stekernkeeping track of irc on the web has one advantage though, when you see some guy saying something you sooo badly want to respond to =P13:14
juliusbyeah like someone posting stuff about the NIOS13:14
stekerndoesn't the normal VCD=1 work for vcd dumping with vlt-tests?13:17
stekernI know I've done that sometime in the past13:17
stekernman, do I hate this proprietary IDE...13:27
juliusboh, not sure VCD=1 works for the vlt tests13:43
juliusbit's easier to just re-run the test by going ../vlt/Vorpsoc_top13:43
juliusband because there's an sram.vmem file there it'll automatically run that13:43
juliusband then you just pass -v I think13:43
juliusband it'll dump to a VCD13:43
stekerndevelopment tool for blackfin13:48
juliusbah ok13:52
juliusbis it buggy or just annoying?13:52
stekernboth :)13:54
stekernit frequently bluescreens this poor windows machine13:54
stekernthe editor is complete shit (not that I would use it anyways)13:55
stekernand right now it's mostly annoying because it is a clicky gui-ide13:56
juliusball of the complaints we receive about our bundled IDE for our DSPs, too:)13:56
juliusbi have been a little bit involved with the tools team here who maintian the IDE and compiler and stuff for the DSP13:57
juliusbso it's interesting to hear the thoughts of someone who actually has to use one of these things13:57
stekernI have this bug that shows at bootup 1/100 times, and I have breakpoints scattered in strategic places to catch it13:57
stekernin order to break, reload the program, and start the program I have to manually perform 3 different 'clicks' (or keystrokes, at least it has hotkeys)13:58
juliusbI don't think ours bluescreens too often, but the editor is considered a joke, and it's really annoying to use in general13:59
stekerninstead of being able to nicely automate it if it'd have some command line tools13:59
mor1kx[mor1kx] juliusbaxter pushed 3 new commits to master:
mor1kxmor1kx/master 9eaa12c Julius Baxter: pronto: remove unnecessary PC signal going from fetch to ctrl unit14:17
mor1kxmor1kx/master 8a1019c Julius Baxter: pronto tcm fetch: cleanup and bugfixes...14:17
mor1kxmor1kx/master 8b077a0 Julius Baxter: documentation: little bit of an update14:17
juliusbhah I'd kicked off a GCC tests run in mor1kx-dev-env, and in the meantime just don a rebase to push my work from last night. It was obviously doing one of the long loop tests, and when it finished the source had changed, and so it re-built the verilator model and continued :)14:22
olofkI want to remove a section from an elf file. Can I use objcopy for that? Does that output elf files?14:22
olofksolved it14:25
olofk(I think)14:25
juliusbobjcopy with -R <sectionname> IIRC from my playing around the other day14:31
glowplug`Have you guys heard of BORPH?
juliusbthat page doesn't say anything about the actual hardware (ie. RTL blocks) involved16:56
juliusbit's missing a lot of very important informatino about what is between the software and the FPGA16:57
stekernyeah, I agree, I don't get at all what it actually does from that17:11
glowplug`Back.  The BORPH creates a file in linux that is the FPGA (the same way our mouse is a file ect.).17:17
glowplug`You can start, stop userland processes in the linux system that reconfigures the FPGA automatically.17:17
juliusbFine. What can it do to that then? Does it have stuff on it already?17:18
stekernyes, that's what the page says. doesn't answer juliusbs questions17:18
stekernthere's a little more info there17:18
juliusbOK, so let's say you program the FPGA - what's the API (presumably some registers or something on the FPGA) to allow interaction between the Linux system/FPGA hardware17:19
glowplug`The best example of BORPH being used is the Rhino project and ROACH.  It simply makes it easier to load and unload IP and also allows you to write applications that communicate between hardware devices using linux (piping ect.).17:19
glowplug`The API is the linux file interaction itself.  =)17:19
glowplug`So outputs from lets say an ethernet ic on the FPGA would be grep'able, pipeable ect.17:20
juliusbAt the software level, maybe, but how does it actually communicate with the FPGA? Shared memory? SPI?17:20
glowplug`How it works under the hood I have no idea yet.  I'm researching it right now.17:20
glowplug`But the possibilities of interfacing with individual hardware blocks as unix files are endless.17:20
juliusbThere's tonnes of this airy-fairy academic FPGA stuff, but very little actually seems very powerful17:21
glowplug`It seems like they have a functional telescope radio that processes many billions of samples per second using it.  And also a functional long range RADAR system.17:22
juliusbThis seems like a sophisticated FPGA programming and communication system put under the Linux kernel's hood. Maybe that's a good place to put it? I don't know, but it seems like a bit of overkill17:23
glowplug`I do agree that academics can produce quite a lot of impractical stuff and make it sound great.  But this is running some serious firepower.17:23
juliusbWell, I only think the mainstream CPU + FPGA thing works if you're selling some commodity accelerator17:24
glowplug`I agree.  It is an overkill in functionality.  But I can see some other great uses for that power to actually simplify things.17:25
juliusbsorry, some commodity accelerator platform - so you have a CPU and say a 16 large-ish FPGAs nearby. You'll certainly need some flexible, easy-to-use mechanism for configuring and communicating with the FPGAs17:25
glowplug`If it could be prepacked in a way that would allow developers to debug openrisc as linux files, load and unload hardware in a way they are already familiar with. ect.17:25
juliusbjust like we have a system of standardising executables on operating systems, and it looks like they've done it here17:25
glowplug`I wish I understood more about how it worked.  O.o17:26
juliusbfor the applications you mentioned, thugh, it seems they could have just done it manually and you would have the same resault17:26
juliusbno doubt this just adds a layer of complexity which I'm not convinced is helpful or even necessary17:26
glowplug`I do agree that it is another layer, but I'm not convinced its a layer of complexity.17:27
juliusbbut if I have an FPGA next to my CPU and I want to, say, quickly encode some video to h.264 or whatever, and I have an app which knows how to interface to that FPGA and configure it and feed it frames to make the job quicker, then sounds good to me.17:27
glowplug`CPython is a layer ontop of C.  But an abstraction layer that reduces complexity.  Hides it from the user.17:27
juliusbhowever we haven't seen this because modern CPUs are full of such accellerators and run at many GHz - orders of magnitude faster than complex maths or data processing can be run on an FPGA, even the fast ones17:28
glowplug`The current FPGA toolchain is extremely complex to most users who are new to the field.  Like C to a Ruby programmer.17:28
juliusbit seems to me that someone must still run the FPGA tool chain at some point to generate the FPGA image17:29
juliusball you're doing is putting the bit that flashes the image onto the FPGA under the hood of Linux17:29
glowplug`I will agree that modern CPU's are faster at serial tasks than FPGA's but they cannot interface with the outside world.  It's a pain in the ass getting 13 IO from a parallel port on a modern PC.17:29
juliusbthat is is the dead-easy part of FPGA design (so long as you have the right physical connections :P)17:29
glowplug`And gate latency in an FPGA is 10ns versus my Ivy Bridge PC that runs my CNC has only sub 10us.  And thats if its not doing something else.17:30
glowplug`Maybe my example was poor too.  Regarding the toolchain.17:30
juliusbI'm not sure the solution to crap I/O on commodity PCs is to put an FPGA next to them17:30
glowplug`I think that doing creative communication and debugging between IP on your FPGA using existing linux tools is the main advantage.17:31
juliusbfine, probably fine-grained real-time I/O control you want an FPGA for17:32
glowplug`You might be right.  But the radio and robotics guys seem to think its the solution. Haha17:32
juliusbMmm I'm of the opinion that the FPGA debug flow is obfuscated enough without adding the Linux kernel to the mix!!!17:32
glowplug`Its a layer of abstracting away complexity though.  Not adding complexity to it.17:33
glowplug`How simple is "this file is my nic, I can cat to it, grep it, output its io to file ect."17:33
juliusbI reckon you could achieve the same with userspace code to an FPGA over a USB-interface17:34
glowplug`That is why linux is so great.  It solves everything by giving you a small subset of primitives and universal control.17:34
glowplug`You could write an application to do it.  I think some exist actually.  But linux tools to interact with files are extremely mature, stable and powerfull.17:36
glowplug`Not to mention almost universally understood.17:36
juliusbI'm saying you could write a user-space application (and driver, admittedly) to instantiate the FPGAs and create character devices for them17:37
juliusbprobably the value in this project is the standardisation of an API, perhaps17:38
juliusbalthough I'm not sure they've even done that... must read more17:38
glowplug`That's what I was reffering to.  A userspace application + kernel module could achieve the same level of functionality no doubt.  But Linux applications can already do anything imaginable to and from a file.17:40
glowplug`I need to read more too.  I don't know the answer to the API thing.17:40
juliusbwell this whole thing relies on the fact you have the hardware. It sounds additional effort (on top of all of the ballache involved in doing FPGA development) to a) run the kernel they're going on about and b) hook up the I/O between whatever is runningg their fancy kernel and the FPGA17:41
juliusbI still don't see why you don't just write a driver and do this over USB17:42
juliusband run it on any old kernel17:42
juliusbwell how are they communicating with this FPGA on the board?17:44
juliusbunless it's PCIE I can't see how USB could be any worse than anything else (SPI/I2C etc.)17:44
glowplug`My guess is LVDS?  I don't know how else they get that bandwidth.17:44
glowplug`Could be PCI-E also.17:45
juliusbLVDS is just a physical interface17:45
juliusbPCIE uses LVDS (I think)17:45
juliusbyou need a protocol to go over the physical interface17:46
glowplug`Actually your right I remember reading that a few days ago on the wikipedia.17:46
glowplug`It probably is PCI-E then.17:46
juliusbBut... it looks like they have 1 FPGA programming another, and the fancy Linux is running on .... that FPGA?17:46
glowplug`It is a PPC SoC running the BORPH kernel that reprograms the Virtex-617:47
juliusbyeah that is silly17:48
glowplug`It does apparently have an API.17:55
glowplug`It creates a kernel thread that handles HWR routines (the api).  When you execute a BOF file it starts a unix process which the kernel thread grabs and configures it then flashes it to the FPGA.17:56
glowplug`Communication is by packets handled by the MKD kernel thread which handles messages from software on the system to gateware on the FPGA.17:58
glowplug`The physical hardware connection is by PLB (peripheral logic bus).  Never heard of it.17:59
glowplug`Also the PPC core IS inside of an FPGA.  Reffered to as the "control fpga".  The PLB is something else.  The bus used to reprogram the "user fpga" is the SelectMAP bus which is a bidirectional 8-bit bus running at 50mhz.18:01
glowplug`The more and more I read I'm starting to agree with you.  That this is a great idea but their implimentation might be a little hairbrained.18:04
stekernif you need 16 virtex-6, you probably actually need more, then I can see the point of a project that makes it supereasy to swap around images to them18:08
stekernPLB is to PPC what wishbone is to openrisc18:10
glowplug`I see.18:13
glowplug`What I'm trying to figure out now is how the RHINO project uses it.  Because they have a Spartan-6.  And their SoC is an ARM Cortex-A8.18:14
glowplug`That is a much more realistic configuration.18:14
stekernwhat's the RHINO project?18:15
glowplug`It is an SDR project that implimented a working RADAR system.18:16
glowplug`Very interesting because the HDL was written in Python using Migen.  And they use BORPH.  Lots of bleeding edge (and possibly not useful) technology.18:17
stekernit's possible it's useful, but me and julius just see the abstraction layer as an obstacle and not an aid18:25
glowplug`For development (and not deployment) that may very well be the case.18:26
glowplug`Be right back.  =)18:26
--- Log closed Tue Mar 26 00:00:25 2013

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