IRC logs for #openrisc Tuesday, 2013-03-26

--- Log opened Tue Mar 26 00:00:25 2013
--- Day changed Tue Mar 26 2013
-!- Netsplit *.net <-> *.split quits: Gentlema`, _franck_, serp_09:06
stekernisn't it beautiful?:
stekernit's still a bit buggy, but dhry on de0-nano says: DMIPS / DMIPS/MHz: 69 / 1.38000020:12
stekernbefore it was 1.1620:13
glowplugNicely done!20:20
glowplugAlso I want to thank you for that link to Migen again I would have never found that.  I'm going to learn it and hopefully I can contribute something soon.  =)20:21
stekernheh, np20:23
stekernI think it could be very useful for building the SoC with it, not sure if I'd do any cores with it though20:26
glowplugIt would lend itself extremely well for glue code.20:26
glowplugMy current goal is to try and impliment an extremely simplistic SIMD vector CPU in Migen.  If the Verilog ends up being totally unusable and horrifying then I will probably strap down and learn Verilog directly.20:27
glowplugThen my goal after that is to try and tie it with mor1kx as a co-processor.  If that is even possible.  Haha20:28
stekernI can't see why it wouldn't, as long as what it does fit's the SIMD instructions20:28
stekernI think that's how juliusb did the FPU in or1200, he took an external floating point core and hooked it up to the FPU instructions20:30
glowplugBut there is no FPU for mor1kx correct?20:30
glowplugAhh ok cool.  I mentioned the idea to him a few days ago and he said that there was no plans for SIMD I wasn't sure if that also meant no FPU.20:30
glowplugIf nobody else is attempting it then I think its a great place to start.  =)20:31
glowplugI can't imagine there would be any benefit to rewriting any instructions so I will just study the OR1200 SIMD instructions.20:31
glowplugTheres no chance of those being re-written for OR2k?20:31
stekernor1200 (implementation) doesn't have simd, or1k (architecture) has ;)20:32
glowplugAhh.  So there is currently NO SIMD implimentation for any OpenRISC core?  What a challenge!20:32
stekernoh, there's probably how ever much room for those being re-written20:32
stekernyeah, no SIMD implementation, not even the simulator supports them20:33
glowplugIccarus has no SIMD support?20:33
stekernI'm achademically very interested in SIMD support (airy-fairy as juliusb put it yesterday), not sure how useful they'd be in reality.20:34
stekernno, not icarus, that's an verilog simulator. I meant openrisc simulators, or1ksim or qemu for instance20:35
glowplugFrom what I understand the ARM cpu's with SIMD can muscle through some really useful tasks that the non SIMD (or slower SIMD) CPU's really shut down with.  For example the i.mx233 is a $5 ARM9 chip it struggles with youtube, fast scrolling, ect.20:35
glowplugThe newer chips (with absolutely no VPU or GPU driver support) can muscle through those kinds of tasks.20:36
stekernyes, but who's going to use openrisc for youtube ;)20:37
glowplugHopefully 8 billion people.  ;)20:37
stekernI get your point though, and I think it'd be cool to have them implemented20:37
glowplugAiry-Fairy.  Haha20:38
glowplugI think he said something similar about academia.  Priceless.  =)20:38
stekernif not for anything else, for the point of reviewing them in the arch spec20:38
glowplugThese things probably are toys in all honesty.  But I like toys.  8)20:38
stekernwell, I'm not *really* academic, only in the sense of wanting to learn about it20:39
stekern+ I'd like to play around with SIMD support in the compilers20:39
glowplugAnother interesting thing is the path that computing is moving in general towards convergance of high speed serial and high parallel.  The Xeon Phi is physical (but expensive) proof that is where computing is headed.20:40
glowplugThats great!  I know very little about compilers and what good is a chip without a good compiler.  =)20:40
stekernI also would want to do a 64-bit implementation, another thing that isn't really 'needed' ;)20:41
glowplugI'm curious about a few things.  32-bit RISC/MIPS CPU's can address more than 4gb of memory correct?20:42
glowplugIntel has "Physical Address Extension" I don't know if there are any RISC implimentations.20:45
stekernwith an MMU, yes20:46
glowplugI think 32-bit is a good place to be then.  Although I do agree 64-bit would be extremely cool to have.  =)20:46
glowplugBefore upping bit-depth things like chip-level software transactional memory could give significantly bigger boosts to code execution.  And things that interface with the Analog world wont see 64-bit conversion for awhile I think.20:48
stekernI agree completely, as I said, only an academic interest =)20:50
glowplugI wonder how much of ARMs reasoning for pushing out 64-bit chips is just popular opinion and pressure.  And not actual technological progress...20:50
glowplugFrom what I understand SIMD cores get to 512 bits wide.  Now THAT would be interesting.  =D20:51
glowplugThat is how intel crams 1TFLOPS double floating point into a single chip @ 200 watts.  O_O20:53
glowplugI am also extremely interested in the architecture of the PS2 game console.  It has vector-float units that can also execute regular CPU instructions.  IT was truly a hybrid CPU/GPU.20:55
glowplugAre there any OpenCores that you are aware of that supports GLSL?21:11
stekernok, modified dcache boots linux in verilator now at least21:41
stekernnot on the de0-nano board at all ;)21:41
stekernjuliusb: can you simulate uart input somehow?21:45
stekernmost certainly you can, if you put enough into it, but can you easily?21:46
juliusbstekern: your waveform is a thing of beauty22:48
juliusbumm good questino about UART input I was thinking about doing it sometime - it would be pretty leet22:48
juliusbit's just C22:48
juliusbwould be easy to sscanf stdin or whatever22:48
juliusbawesome work, btw, getting the cappuccino verilator-friendly22:53
juliusbi'm attempting to get freertos running on prontoespresso22:53
juliusbit runs, at least22:53
juliusblooks good22:53
juliusbi think the issues are software, not hardware22:53
juliusbit assumed the wrong way to clear interrupts, that was one thing22:54
juliusbotherwise it was all good22:54
juliusbonly 1 instruction in delay slot (admittedly a critical one :P) which was a problem22:54
juliusbbut.. otherwise it looks like it kind-of runs doing what it should22:54
juliusb(I'm also running it in the cycle-accurate model)22:54
--- Log closed Wed Mar 27 00:00:48 2013

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