IRC logs for #openrisc Sunday, 2013-03-24

--- Log opened Sun Mar 24 00:00:36 2013
Gentlema`Hello.00:54
glowplugGood afternoon.  =)01:20
glowplugI found an SDR project on github.  https://github.com/NBitWonder/SDR01:23
Gentlema`How interesting.02:46
Gentlema`Sorry, I did not see your reply.02:46
Gentlema`I finally made it out today.02:46
Gentlema`Considering of where we are, I do think that the FPGA approach is better than the micro approach to SDR.02:49
glowplugYeah Its really unfortunate that he decided to use a PIC for that project.02:51
Gentlema`It does appear to limit its capabilities.02:51
glowplugSeverely.02:52
Gentlema`The farmers here got fed up and cleared a path themselves about six feet wide.02:53
Gentlema`Snow piled precariously.02:53
glowplugI'm surpirsed there are farmers there!  I wonder how long their grow season is...02:54
Gentlema`We are in the northern end of the breadbasket.02:57
Gentlema`The soil here is fairly fertile as well.02:57
Gentlema`In fact, the mojority of potash is mined from this area.02:58
Gentlema`*majority.03:00
Gentlema`Also, uranium.03:00
glowplugAre you joking or being serious?  Haha03:03
Gentlema`Serious.03:04
glowplugThat is epic...03:04
glowplugOnesecond have to reboot.03:04
glowplugBack.03:09
Gentlema`*That* was far longer than one second...03:09
Gentlema`Saskatchewan has ~40% of the World's Uranium.03:10
glowplugLearn something new every day.  8)03:15
Gentlema`Indeed...03:17
glowplugHave you learned anything about the memory controller?03:36
Gentlema`I have learned some about the memory controller.03:41
Gentlema`I am currently attempting to get stekern's tools to build.03:41
glowplugI see.  What kind of issues are you running into?03:43
Gentlema`At the moment undefined functions from either within the project or dependiencies from one of stekern's other projects...03:45
stekernGentlema`: can you paste the errors?03:47
Gentlema`or1ktrace.c: In function 'or1ktrace_init':03:48
Gentlema`or1ktrace.c:316:28: error: 'bfd_arch_or1k' undeclared (first use in this function)03:48
Gentlema`or1ktrace.c:316:28: note: each undeclared identifier is reported only once for each function it appears in03:48
Gentlema`or1ktrace.c:321:48: error: 'print_insn_or1k' undeclared (first use in this function)03:48
Gentlema`make[1]: *** [libor1ktrace_la-or1ktrace.lo] Error 103:48
Gentlema` 03:48
glowplugThe best way to paste errors is to use http://tny.cz/03:54
glowplugThat way you don't lose formatting and it takes up less space on IRC.  =)03:54
glowplugWhy would there be an undeclared variable?  O.o03:56
stekernoh, that's juliusb tools ;)03:56
Gentlema`Sorry.03:58
Gentlema`I transposed names.03:58
stekernGentlema`: did you build the toolchain like this? http://opencores.org/or1k/OpenRISC_GNU_tool_chain#Newlib_toolchain_.28or1k-elf.2903:58
mor1kx[mor1kx] skristiansson pushed 2 new commits to master: https://github.com/openrisc/mor1kx/compare/1f666b95d88f...dbc447518fca04:27
mor1kxmor1kx/master 884da83 Stefan Kristiansson: icache: remove bypass leftovers04:27
mor1kxmor1kx/master dbc4475 Stefan Kristiansson: dcache: change local parameters to localparam04:27
stekernwhat a relief, none of the mmu changes have decreased fmax (actually increased it slightly)04:37
stekerntimequest reports 82.37 as fmax on the de0-nano04:37
stekernwith mmus disabled04:38
stekernaround 72 Mhz with them enabled04:38
stekernand then the critical path goes from dmmu->wb-bus->rf04:39
stekernthrough dcache04:39
stekernwhich is the next thing on my list to go through04:40
stekernis it me or verilator that is stupid? this patch fixes what verilator considers a comb-loop: http://pastie.org/709713407:58
stekernis it because of the blocking statements in the pre-patch case?08:25
juliusbhmmm, yeah, strange!10:35
stekernjuliusb: still around? why do I get "%Warning-WIDTH"s even though I use "-Wno-WIDTH"?11:46
stekernthis is in execute_alu, so I assume you get around that11:48
juliusbpastie?11:57
stekernhttp://pastie.org/709858012:01
stekernand I run it with: make vlt-tests USER_VLT_FLAGS="-Wno-WIDTH"12:02
juliusbhmm odd - what default for the divider are you using?12:14
juliusberr I mean what parameter are you passing?12:14
juliusbjust try putting the /* verilator lint_off WIDTH */ around it12:15
juliusbbtw I'm verilator version: Verilator 3.841 2012-09-03 rev verilator_3_84112:15
stekern3.820 here12:18
stekernI think I'm using the serial and cmov enabled12:18
juliusbThe way we call verilator in orpsoc/mor1kx-dev-env is like so:12:18
juliusbverilator -language 1364-2001 --top-module orpsoc_top -Mdir . --sc \12:18
juliusb --trace --exe --inline-mult 1 -O3 -x-assign unique -I/work/mor1kx-dev-env/boards/generic/mor1kx-prontoespresso/sim/run/../../../../../bench/sysc/include -I/work/mor1kx-dev-env/boards/generic/mor1kx-prontoespresso/sim/run/../../../../../bench/sysc/src \12:18
juliusb-f /work/mor1kx-dev-env/boards/generic/mor1kx-prontoespresso/sim/run/../../sim/vlt/verilator.scr12:18
juliusbno -Wno-*12:19
juliusb(nothing passed in the verilator.scr either)12:19
stekernyeah, but the USER... get passed somewhere, because if I do -Wno-BLAH it errors with unknown option12:20
juliusboh.. the USER stuff gets exported? Let me look...12:20
juliusbnope, no -Wno-* stuff anywhere in the verilator makefile12:22
juliusbmaybe hard to understand exactly why this is happening, but just do the annoying thing and put the lint_off comments around it12:22
juliusbI'm happy to have that committed12:22
juliusbit's a known shortcoming in Verilator's linting12:23
juliusb(if the parameter passed is a different string length to the one defined as the default in the module, this will fail linting)12:23
stekernyeah, and we'll be able to catch real width errors12:24
juliusbyep12:24
juliusbman I need to buy Wilson Snyder a beer if I ever meet him - this is a very good tool isn't it?12:24
juliusbjust the fact it's a good lint tool is enough12:25
juliusbso i'll buy him a beer for that feature, and a beer for the cycle-accurate C model bit12:26
juliusb:)12:26
stekern"it's an annoying bitch, but a good annoying bitch" to quote you (I think) ;)12:30
juliusbCertainly12:30
juliusbthe quality of the code and design is better for it12:31
stekernnext problem: undefined references to set_mem32 and getGpr14:07
stekernI know I've encountered that before, but no what the solution was...14:08
juliusbmmmm14:11
juliusbin the cappuccino pipeline?14:11
juliusbor in the systemc stuff?14:11
stekernin the systemc stuff14:13
stekernI get that in espresso too14:13
stekernthey are suppose to be in a OrpsocMemoryAcces14:16
stekernah, it's this stupid problem that files change name if the content change14:47
stekernthe gnerated files14:48
stekernthis need to be fixed once for all14:55
glowplugHave you guys talked about adding SIMD to mor1kx?20:58
juliusbthe vector data instruction set in the OR1K architecture?21:52
glowplugExactly.  For parallel computation and basic 3d operations ect.21:53
juliusbit's not critical, or on the plan21:53
juliusbso, not much thought for it- but please, have a go :)21:53
juliusbit wouldn't be that hard21:53
glowplugThere is some SIMD work in the ORSoc graphics core which is in Verilog.21:53
glowplugI'm still trying to learn the basics though.  I think I would be really interested in attempting that.  =)21:54
stekernjuliusb: I've hacked OrpsocMor1kxAccess and OrpsocMemoryAccess to not depend on those numbers.21:56
stekernit's not so pretty, and can potentially slow down since it now references through orpsoc_top and down to the modules21:57
stekernbut however ugly it is now, it's still prettier than constantly have to change those includes and classes etc...21:57
stekernI'll clean it up tommorrow and send it to you21:59
juliusbok, sounds good21:59
juliusbit never bothered me too much as it rarely changed22:00
stekernhow have you put up with changing those numbers around for so long?? ;)22:00
juliusbI did it only like 3 times all up!22:03
stekernheh, ok22:03
stekernmaybe it's me tinkering with stuff to much so they change a lot...22:03
stekerns/to/too22:04
stekernanyway, I'm sleep deprived, have to go to bed. I almost went already at 21:00, but remembered that I hadn't put together my invoices for the bookkeeper and she needs it tomorrow.22:05
stekernbut when that was done, sitting by the computer and having a nagging problem was too much to resist...22:06
glowplugHaha22:07
glowplugHave a good sleep and dont let the "bugs" keep you up.  =)22:07
juliusb:)22:07
juliusbI know the feeling22:07
juliusbmor1kx didn't really need a single-cycle ROM fetch unit22:08
juliusbbut, i would like it22:08
juliusbso22:08
juliusbhave almost finished it :)22:08
juliusbpronto-espresso, specifically22:09
asmok, today's goal22:13
asmget linux running on my de0 nano22:13
* asm gets excited22:13
juliusb:)22:13
asmI'm going to start here: http://ec2-122-248-210-243.ap-southeast-1.compute.amazonaws.com/mediawiki/index.php/UClinux22:14
asmunless you guys have some other recomendations22:14
juliusberm22:15
juliusbyou realise you're in #openrisc?22:15
asmya22:15
asmhaha, excellent point22:15
asmis the a good tutorial on getting linux on the openrisc core?22:15
juliusband the page you just posted talks about using some horrible proprietary shite from Altera?22:15
asmyeah :(22:15
glowplug=(22:15
asmnios222:15
* asm googles again22:16
glowplugNIOS 2 is our enemy.  Haha22:16
juliusbbut... haha, yes I'm not sure there's a nice easy guide for the de0 nano22:16
juliusbmy goal for the weekend was to do a guide for running FreeRTOS on the DE0 nano22:16
juliusbbut I wrote a single-cycle ROM fetch unit for the mor1kx instead :(22:16
asmwell, ok, I'll start over22:16
juliusbbut I will prepare something like that for the chiphack.org22:16
juliusbevent22:16
asmmy real goal is to get mruby on the de0-nano22:16
juliusbso if you check back ni a few weeks the FreeRTOS tutorial should be avialable22:17
asmI was thinking of using uclinux + nios222:17
asmbut I'd love to use openrisc22:17
glowplugYou should look into Topaz > Mruby although it is very infant.22:17
glowplugFor embedded development.22:17
asmdur, it's written in python?22:18
asmyou're talking about this? http://docs.topazruby.com/en/latest/blog/announcing-topaz/22:18
glowplugasm do you plan on learning Verilog and actually modifying the fpga ip?22:18
asmglowplug: eventually22:18
asmI'd like to write custom vhdl <-> ruby bindings22:19
glowplugIts not really written in Python. Its RPython and it compiles Ruby into C at runtime through something called the JIT.22:19
asmthat seems far overblown at the moment22:19
asmmruby is just simple c22:19
asmbbiab22:19
glowplugIts actually extremely underblown.22:19
glowplugYou write Ruby.  Run translator and it generates C magically.22:19
glowplug=)22:19
glowplugThere are some things to consider though.  Firstly at the processing power of openrisc/nios2 is not enough for mruby/topaz ect.22:21
glowplugI would suggest that if you want to do embedded Ruby development for now you need a very fast embedded CPU.  Like an imx233.22:23
glowplugAnd if you want to do RTL type stuff seperately on the Nano.  Then merge them at a much later date when its realistic.22:24
glowplugThis is the best board for doing Ruby in tiny systems at the moment.  https://www.olimex.com/Products/OLinuXino/iMX233/iMX233-OLinuXino-MICRO/22:25
glowplugHere is a really great article that explains why RPython (and Topaz) are fundamentally different than regular interpreters (like mruby).22:43
glowplughttp://tratt.net/laurie/tech_articles/articles/fast_enough_vms_in_fast_enough_time22:43
asmback22:56
asmreading your links22:56
asmthat's not a bad little board22:56
asmbut the raspberry pi is far better22:57
asmand cheaper22:57
glowplugThe board I linked can be homebuilt for $15.  Also the RPi is our enemy.22:57
asmoh dear22:57
asmyou guys have too many enemies :P22:57
glowplugThey have a bad history about being dishonest about their product.22:58
glowplugContrary to popular belief the RPi is a very closed system.22:58
asmindeed22:58
asmbut it's an important first step22:59
asmregardless, I'm not here to talk about embedded systems22:59
asmI want to see fpgas running more applications22:59
asmand more accessable22:59
glowplugFPGA's are bad at running serial applications.22:59
asmvery true23:00
asmand this is why I think they're the future23:00
glowplugThe reason we develop on FPGA's is because we cannot fabricate our own semiconductor chips (yet).23:00
asmyup, now it's time to think out of the box23:00
glowplugIt would be exceptional if FPGA's could run at 1.6ghz.23:00
glowplugBut it's simply not possible.23:01
asmand they will soon23:01
asmnot to mention they'll have more and more LEs23:01
glowplugFPGA architectures are proprietary.23:01
asmbut think about the paradigm shift in the macroprogramming world23:01
asmprogrammers are no longer coding serial systems23:01
asmwe have parallel and async systems to work with now23:02
asmwouldn't it be nice if these systems ran on fpgas?23:02
glowplugSIMD devices.  Absolutely.23:02
glowplugNo it would be horrible.  Haha23:02
asmtoday it's horrible23:02
asmsure23:02
glowplugFPGA's are only good for 1. designing systems 2. low volume systems that need to change constantly23:02
asmand 2 is the key23:02
asmthink about what the average computer is doing23:03
glowplugThe average computer is roughly five million times more efficient than an FPGA + NIOS2.23:03
asmtoday it is23:03
glowplug=)23:03
glowplugThere are a lot of problems with assuming that FPGA's will surpass ASIC's.23:04
glowplugFor example.  Xeon Phi boards yield 1TFLOPS double float at 200 watts.23:04
glowplugThat number is only going to go up... fast..23:04
asmbut it's not going up because of advances in chipmaking23:04
glowplugCurrently embedded processors on FPGA's are many billions of times less efficient.23:05
asmcurrently23:05
glowplugThat gap will widen.23:05
glowplugWith the ASICs getting more and more ahead of FPGA's.23:05
asmthe asics are only changing their architecture23:05
asmthe chip tech isn't changing23:06
asmwhereas fpgas have a long way to go23:06
glowplugPhi is 50 Ivy Bridge cores at 1.2ghz.23:06
glowplugOn a single chip.23:06
asmimagine if intel put that kind of effort into fpgas23:06
glowplugIf FPGA's ever come within a million times as efficient.  It would take 200 years.23:06
asmthink about where we were 200 years ago23:07
asmI'd say you're off a few :)23:07
glowplugI know that technology improves over time.23:07
glowplugBut ASIC performance will always scale faster than FPGA.23:07
asmyes, for a single purpose23:07
glowplugAn FPGA with a serial processing core is a single purpose processor.23:08
asmindeed23:08
asmbut what if it could reconfigure itself based on its workload23:08
asmsuddenly, it's far more efficient23:09
glowplugThere are firms working on that.  But the benefits are maybe 1-2 times.  Not the billion times that it would need.23:09
asmI have a perfect example on my desk23:09
asmI have a top of the line intel cpu23:09
glowplugAlright.23:23
asmit's hash rate of sha256 is about 1 mega hash/s23:23
asmfiring on all cores23:23
glowplugDo you know what the most efficient and fastest sha256 core is on the planet?23:23
glowplugIt's an ASIC.  =)23:23
glowplugBy about a factor of 1,000 compared to FPGA's.23:23
asmin the machine next to it, I have 8 gpus23:23
asmthey each have about 1024 vector cores23:23
asmthis machine can do about 500-700gh/s23:23
asmerr mega23:23
asmhold on I'm getting there23:23
asmon my desk is an fpga doing about 300mh/s using a trivial amount of power23:23
glowplugRight.23:23
asmand the avalon asic system is doing something in the gh/s range23:23
glowplugAnd there is an ASIC chip that gets 65gh/s using less power than your FPGA.23:23
asmmy point here is this: the fpga is certainly not the fastest system at hashing23:23
glowplugIt will never be physically possible for an FPGA to be even within an order of magnitude of an ASIC for any task.23:23
glowplugThe ultimate goal for designing open source processors, graphics cards, network controllers, is to have those cores made into ASICs.23:23
glowplugFlashing them to FPGA's is an intermediary development stage.23:23
glowplugFPGA's themselves are an intermediary technology.23:23
-!- Netsplit *.net <-> *.split quits: ams, heroux23:23
-!- Netsplit *.net <-> *.split quits: jonmasters23:24
asmdoh, irc hiccup23:24
glowplugInteresting....23:26
asmhttp://opencores.org/or1k/FPGA_Development_Boards#Pre-built_image_with_orpsoc.2C_U-Boot_and_Linux23:27
asmnice23:27
glowplugAt any rate.  You should look into the homecmos project.  The goal is to open up the technology for fabricating ASIC's to the masses.  Totally eliminating proprietary FPGA's from the picture.  Open design => Open hardware with no middleman.23:27
asmthat would be nice23:28
glowplugIt would truly cause a paradigm shift.  Infact it would be possible to fabricate FPGA's with an open architecture to fulfill niche markets (like motion control and software defined radios ect.).23:35
glowplugBut FPGA's themselves are a solution to only a very small amount of problems.  And they scale very poorly.23:35
glowplugIf you are interested in getting heavily involved in processor design (asic OR fpga) you should research all of the tools on this site.  http://opencircuitdesign.com/verilog/index.html23:35
asmperhaps, but let's just disagree for now :)23:35
-!- Netsplit over, joins: heroux23:35
asmthanks!23:35
glowplugLet me put it this way.  Altera and Xilinx are not capable of what you describe.  But if you want to design such an FPGA do so in Verilog and have it made into an ASIC (which an FPGA is, oddly).  You can use VTR as a design basis and sythesis toolchain.  https://code.google.com/p/vtr-verilog-to-routing/23:46
asmI'm not interested in building asics for now23:46
glowplugIf thats true then you will never see FPGA's as fast as you want.  Unfortunately.23:46
glowplugI would very much like for that to be possible.23:46
glowplug`Did I just get booted?23:50
juliusbthe server's going crazy23:50
-!- Netsplit *.net <-> *.split quits: simoncoo1, nollan, _franck_, serp__, larks, larks_, jonmasters_, stekern, orsoc1_, Amadiro, (+14 more, use /NETSPLIT to show all of them)23:58
--- Log closed Mon Mar 25 00:00:41 2013

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