| jeremybennett | juliusb: Thank you very much | 10:21 |
|---|---|---|
| juliusb | Are you coming to OSHUG tomorrow? | 10:52 |
| jeremybennett | jeremybennett: Yes - with a DE0-nano for you | 10:53 |
| juliusb | Oh, great! | 10:55 |
| juliusb | I'm looking forward to it, there's some interesting talks | 10:56 |
| hno | git.openrisc.net IPv6 address seems non-operational. | 14:12 |
| jonibo | yeah, I know... will look into when I get a chance | 14:13 |
| andresjk | hi | 19:14 |
| andresjk | does ORPSoC supports DMA? I havent seen the peripheral in verilog but I think the ethernet rtl controller uses some kind of dma.... or its just wishbone block transactions? | 19:17 |
| LoneTech | andresjk: there's currently not a DMA controller in it, but a few peripherals do bus master (ethernet, SD) | 19:37 |
| LoneTech | there's a wishbone DMA block in an opencores project | 19:37 |
| andresjk | Im actually reading the documentation. Is it supported I mean does it has drivers for linux? | 19:40 |
| LoneTech | I don't know | 19:42 |
| andresjk | I actually going to design an image processing peripheral which its going to manage a lot of data. Do you think its better to do it as a bus master or use the DMA that you said? | 19:43 |
| LoneTech | andresjk: probably bus master, it's not that hard to write the logic, and the dma block would have really poor performance unless you set it up with multiple buses, which will eventually confuse someone. | 20:22 |
| andresjk | and in the software side, the driver should be a block driver right? I have written a char user-space driver for the gpio but I guess its very CPU demanding. What do you recommend? | 20:25 |
| _franck_ | your driver can be a char driver or you can do a userspace driver (using mmap I guess). If you have a master peripheral, there won't be CPU overhead while transfering data | 22:19 |
| _franck_ | because your peripheral will do DMA | 22:20 |
| andresjk | _franck_, when you said that the peripheral will do DMA you mean that the wishbone logic of the peripheral will have to be based on BLOCK transfer cycles instead for just read/write transactions like the gpio? | 23:34 |
| andresjk | _franck_, btw I did what you toldme last time and it work perfectly but I'm not sure if scaling the gpio for more registers its the best way to design an intensive data peripheral | 23:37 |
| andresjk | DMA block its out of the table which is good. Thanks LoneTech & _franck_ | 23:38 |
| _franck_ | if your peripheral is a wishbone master, it will read/write data to/from other wishbone slaves without need of the CPU | 23:47 |
| _franck_ | you could have registers in your wisbone master peripheral in order to tell it where to stream data out for example | 23:49 |
| _franck_ | and when to start/stop | 23:49 |
| andresjk | so I could have some registers within the peripheral with the first memory address and the last and the master peripheral could retrieve the data from the corresponding RAM segment | 23:58 |
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