| andresjk | I guess that if I design my peripheral that way. Using block r/w cycles and I transfer a lot of data I don't have to be worry about stalling the bus because every 5 clocks It will stop | 00:02 |
|---|---|---|
| _franck_ | you won't stalling the bus as you'll use a bus arbiter | 00:10 |
| _franck_ | then you can assign some determined bandwith to your peripheral and you CPU can still access to the RAM | 00:11 |
| andresjk | nice | 00:13 |
| andresjk | _franck_, whats the easier master peripheral to start? eth_wishbone.v seems like a little more complex to begin with. Or should I start from zero and use Wishbone B4 guidelines? | 00:15 |
| _franck_ | you should start from the spec, then take a look at what other do | 00:19 |
| _franck_ | for master example you also have vga controllers | 00:19 |
| andresjk | Alright, thanks a lot _franck_ and LoneTech ! I'm going to get hands on hdl now | 00:26 |
| asm | https://github.com/jbangert/trapcc wow | 23:06 |
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