IRC logs for #openrisc Thursday, 2013-02-21

andresjkI guess that if I design my peripheral that way.  Using block r/w cycles and I transfer a lot of data I don't have to be worry about stalling the bus because every 5 clocks It will stop00:02
_franck_you won't stalling the bus as you'll use a bus arbiter00:10
_franck_then you can assign some determined bandwith to your peripheral and you CPU can still access to the RAM00:11
andresjk_franck_, whats the easier master peripheral to start? eth_wishbone.v seems like a little more complex to begin with. Or should I start from zero and use  Wishbone B4 guidelines?00:15
_franck_you should start from the spec, then take a look at what other do00:19
_franck_for master example you also have vga controllers00:19
andresjkAlright, thanks a lot _franck_  and LoneTech ! I'm going to get hands on hdl now00:26
asm wow23:06

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