IRC logs for #openrisc Thursday, 2012-12-13

juliusb_franck_: wow, very cool man. no GDB recompile hey? that's awesome00:08
_franck_no recompile00:11
_franck_I'll try to prepare some patches next days00:13
_franck_still need some clean up and tests00:13
juliusbbut this sounds great :)00:14
_franck_our openocd port is now pretty good00:14
juliusbthat's awesome00:14
juliusbgood debug infrastructure is critical00:14
_franck_Marek did a great job too00:15
juliusbyou boys deserve a beer :)00:15
_franck_thanks :)00:15
_franck_we still need to apply my RTL patch to get things works00:15
juliusbstekern: I'm playing with versioning of mor1kx00:42
juliusbfor the implementation version, do we want to shoot for an overall version or pipeline versions?00:42
juliusbI'm thinking VR2 version field (24-bit) should be an overall core release version00:44
juliusb{8'dmajor, 8'dminor, 8'dreserved}00:44
juliusbISRs can perhaps hold what pipeline it is00:45
juliusbie, core config00:45
juliusbok, how about00:45
juliusb{8'dmajor, 8'dminor, 8'drevision} where the revision is a locally modifiable build ID00:46
juliusbbut all releases set it to zero00:46
juliusbmore of a "build" number00:47
juliusbOK I've just seen my first RTL model spit out that it's OR1k 1.0 compliant02:13
juliusbthis must be a real thing now :)02:13
juliusbso I'll push the spec to the repo tomorrow02:13
ErantCan someone explain to me where the bootrom gets mapped on the orpsoc?07:02
ErantI wrote this minimal bootrom, that just prints out '>Hello!' (, but even that doesn't work. I tried the f0 start address, and the 00 start address.07:07
Erant(I'm running on an Atlys board)07:10
stekernErant: which orpsoc are you using?08:23
stekernand regarding delay-slots, or1200 has them, and you are not handling them in the asm08:27
stekernand you should poll the TX being free before putting anything new in that register08:27
stekernsomething like this:
stekernjuliusb: what did you mean by 'ISRs can hold what pipeline'?09:21
stekernjuliusb: heads up: I'm moving the dcache into the lsu, because I think contrary to what that sounds like, it will lead to more modularity10:30
stekernbecause I'm thinking about 'dumbing' the cache down a bit and let the lsu do the thinking and just hand the cache what it needs10:31
stekernthat way the lsu can handle all the pipeline specific tasks, and the cache can just be a cache10:32
stekernin the long run, something similiar could be done with the icache10:32
stekernmove it completely into the fetcher and just have a good 'abi' into the cache10:33
stekernthat pipeline implementations can connect into without having to do things a certain way10:34
stekerne.g. have a 'next_adr_i' input that goes to the tag and cache mems and a 'curr_adr_i'10:35
stekernI'll start with the dcache and we'll see what falls out, because I anyway need to change it to be able to get 1-cycle loads out of it without connecting the adder_result straight out on the wishbone bus10:37
Erantstekern: Eh, I figured the FIFO's like 16 entries deep, and I can stand to not check it.18:07
Erantstekern: Using orpsocv2, the reason I'm asking about the mapping of the bootrom is that the start address seems to be 0xf0000100, but the rom seems to be mapped at 0xf0000000. I don't have a vector at 0xf0000100.18:09
Erantstekern: I had apparently forgotten that jal's also have a delay slot. My bad. It should still work, but I'm getting nothing on the serial.19:18
ErantI've tested the board with a prebuilt .mcs of an orpsoc with a Linux payload, and that works fine.19:18
poke53281Is there any official bug reporting site for the /arch/openrisc tree of Linux?21:30
poke53281or just the mailing list21:32
juliusbthe mailing list is a good place21:48
jeremybennettpoke53281: You can use http://bugzilla.opencores.org21:49
jeremybennettIt has a place for Linux bugs and by default they should go to Jonas Bonn, who maintains OpenRISC Linux.21:49
poke53281Seems like a new account is needed. The Opencores account does not work.21:54
poke53281"User account creation has been restricted. Contact your administrator or the maintainer (Jeremy Bennett ) for information about creating an account. "21:55
jeremybennettYou have to create the account using your address.21:55
poke53281I have an account and I used the same email21:56
jeremybennettHo hum - all email addresses are supposed to be automatically accepted. What is yours and I'll put it in manually.21:57
poke53281I have send you the email in a private message21:58
jeremybennettThanks, but it is your email address I need, not your private one.21:58
poke53281Arghh, thanks. I forgot that I have one22:00
jeremybennettWere you able to register with that one OK?22:04
poke53281Yes, everything works. Writing the bug report.22:09
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juliusbstekern: I meant, by ISRs... that the ISRs (implementation-specific registers) can hold CPU-specific stuff, like info about the pipeline, implementation options etc.23:38
juliusbstekern: dcache into LSU, no probs :)23:39
juliusbthat's actually a very good idea23:39

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