| juliusb | _franck_: wow, very cool man. no GDB recompile hey? that's awesome | 00:08 |
|---|---|---|
| _franck_ | no recompile | 00:11 |
| _franck_ | I'll try to prepare some patches next days | 00:13 |
| _franck_ | still need some clean up and tests | 00:13 |
| juliusb | nps | 00:14 |
| juliusb | but this sounds great :) | 00:14 |
| _franck_ | our openocd port is now pretty good | 00:14 |
| juliusb | that's awesome | 00:14 |
| juliusb | good debug infrastructure is critical | 00:14 |
| _franck_ | Marek did a great job too | 00:15 |
| juliusb | you boys deserve a beer :) | 00:15 |
| _franck_ | thanks :) | 00:15 |
| _franck_ | we still need to apply my RTL patch to get things works | 00:15 |
| juliusb | stekern: I'm playing with versioning of mor1kx | 00:42 |
| juliusb | for the implementation version, do we want to shoot for an overall version or pipeline versions? | 00:42 |
| juliusb | I'm thinking VR2 version field (24-bit) should be an overall core release version | 00:44 |
| juliusb | {8'dmajor, 8'dminor, 8'dreserved} | 00:44 |
| juliusb | ISRs can perhaps hold what pipeline it is | 00:45 |
| juliusb | ie, core config | 00:45 |
| juliusb | ok, how about | 00:45 |
| juliusb | {8'dmajor, 8'dminor, 8'drevision} where the revision is a locally modifiable build ID | 00:46 |
| juliusb | but all releases set it to zero | 00:46 |
| juliusb | more of a "build" number | 00:47 |
| juliusb | OK I've just seen my first RTL model spit out that it's OR1k 1.0 compliant | 02:13 |
| juliusb | this must be a real thing now :) | 02:13 |
| juliusb | so I'll push the spec to the repo tomorrow | 02:13 |
| Erant | Can someone explain to me where the bootrom gets mapped on the orpsoc? | 07:02 |
| Erant | I wrote this minimal bootrom, that just prints out '>Hello!' (http://pastebin.com/FjZ1JaDY), but even that doesn't work. I tried the f0 start address, and the 00 start address. | 07:07 |
| Erant | (I'm running on an Atlys board) | 07:10 |
| stekern | Erant: which orpsoc are you using? | 08:23 |
| stekern | and regarding delay-slots, or1200 has them, and you are not handling them in the asm | 08:27 |
| stekern | and you should poll the TX being free before putting anything new in that register | 08:27 |
| stekern | something like this: http://pastebin.com/E2UTpvur | 09:01 |
| stekern | juliusb: what did you mean by 'ISRs can hold what pipeline'? | 09:21 |
| stekern | juliusb: heads up: I'm moving the dcache into the lsu, because I think contrary to what that sounds like, it will lead to more modularity | 10:30 |
| stekern | because I'm thinking about 'dumbing' the cache down a bit and let the lsu do the thinking and just hand the cache what it needs | 10:31 |
| stekern | that way the lsu can handle all the pipeline specific tasks, and the cache can just be a cache | 10:32 |
| stekern | in the long run, something similiar could be done with the icache | 10:32 |
| stekern | move it completely into the fetcher and just have a good 'abi' into the cache | 10:33 |
| stekern | that pipeline implementations can connect into without having to do things a certain way | 10:34 |
| stekern | e.g. have a 'next_adr_i' input that goes to the tag and cache mems and a 'curr_adr_i' | 10:35 |
| stekern | I'll start with the dcache and we'll see what falls out, because I anyway need to change it to be able to get 1-cycle loads out of it without connecting the adder_result straight out on the wishbone bus | 10:37 |
| Erant | stekern: Eh, I figured the FIFO's like 16 entries deep, and I can stand to not check it. | 18:07 |
| Erant | stekern: Using orpsocv2, the reason I'm asking about the mapping of the bootrom is that the start address seems to be 0xf0000100, but the rom seems to be mapped at 0xf0000000. I don't have a vector at 0xf0000100. | 18:09 |
| Erant | stekern: I had apparently forgotten that jal's also have a delay slot. My bad. It should still work, but I'm getting nothing on the serial. | 19:18 |
| Erant | I've tested the board with a prebuilt .mcs of an orpsoc with a Linux payload, and that works fine. | 19:18 |
| poke53281 | Is there any official bug reporting site for the /arch/openrisc tree of Linux? | 21:30 |
| poke53281 | or just the mailing list | 21:32 |
| juliusb | the mailing list is a good place | 21:48 |
| jeremybennett | poke53281: You can use http://bugzilla.opencores.org | 21:49 |
| jeremybennett | It has a place for Linux bugs and by default they should go to Jonas Bonn, who maintains OpenRISC Linux. | 21:49 |
| poke53281 | Thanks. | 21:50 |
| poke53281 | Seems like a new account is needed. The Opencores account does not work. | 21:54 |
| poke53281 | "User account creation has been restricted. Contact your administrator or the maintainer (Jeremy Bennett ) for information about creating an account. " | 21:55 |
| jeremybennett | You have to create the account using your opencores.org address. | 21:55 |
| poke53281 | I have an account and I used the same email | 21:56 |
| jeremybennett | Ho hum - all opencores.org email addresses are supposed to be automatically accepted. What is yours and I'll put it in manually. | 21:57 |
| poke53281 | I have send you the email in a private message | 21:58 |
| jeremybennett | Thanks, but it is your opencores.org email address I need, not your private one. | 21:58 |
| poke53281 | Arghh, thanks. I forgot that I have one | 22:00 |
| jeremybennett | Were you able to register with that one OK? | 22:04 |
| poke53281 | Yes, everything works. Writing the bug report. | 22:09 |
| -!- Netsplit *.net <-> *.split quits: freakazoid0223, poke53281 | 22:34 | |
| -!- Netsplit over, joins: poke53281 | 22:37 | |
| -!- X-Scale` is now known as X-Scale | 22:42 | |
| -!- Netsplit *.net <-> *.split quits: _franck_ | 22:47 | |
| juliusb | stekern: I meant, by ISRs... that the ISRs (implementation-specific registers) can hold CPU-specific stuff, like info about the pipeline, implementation options etc. | 23:38 |
| juliusb | stekern: dcache into LSU, no probs :) | 23:39 |
| juliusb | that's actually a very good idea | 23:39 |
Generated by irclog2html.py 2.15.2 by Marius Gedminas - find it at mg.pov.lt!