IRC logs for #openrisc Tuesday, 2012-12-04

-!- erant is now known as Erant00:34
ErantI'm trying to build the orpsocv2 for a xilinx board, but for some reason I keep getting "Macro reference `OR1200_OR32_LWS is not defined" from XST.00:34
ErantI'm running the 14.3 version of the Xilinx tools, is that unsupported?00:35
ErantActually. There's an outdated or1200_defines.v in the atlys directory.00:53
ErantIs there a known svn tag where the Atlys board worked?00:55
@juliusbErant: just update the or1200_defines to the newest version02:52
@juliusbolofk: hah, yep I like that one the best :)02:55
@juliusbolofk: I think your pi has been pretty stable, I haven't noticed any disconnects03:00
Erantjuliusb: Yeah, there's other stuff that seems to have gone out-of-sync.04:19
ErantTrying to repair, we'll see if I can make it work.04:19
ErantAt least I know it's not my tools being wonky.04:19
stekernolofk: yeah, I found it myself yesterday, as an addition to the daily dilbert.com05:17
stekernyours is good too, soon I've got nothing else to do than read geeky webcomics ;)05:17
stekernErant: lemme take a look, that LWS thing sounds like I'm partly responsable for breaking05:19
stekernErant: Should be fixed in svn now06:31
stekernthanks for letting us know06:32
mor1kx[mor1kx] skristiansson opened pull request #2: Connect lsu address directly to ALU adder (master...for-openrisc)
stekernjuliusb: a daily dose of patches for you to digest ;)07:49
stekernI reckon the trade off on resource usage/speed is pretty good on that, I got 0.2% resource increase and 23% fmax increase when test synthesising cappucino on cyclone iv before and after applying that07:51
stekernsorry, 13% fmax increase07:53
stekernso ungodly cold here so I can't hit the right keys...07:54
@juliusbstekern: looks good, will have a read through soon11:48
stekernI can run some more tests synthesis on the espressos if you'd like, but I think that should make sense on them11:52
stekernsim tests (of course) passes with it11:52
stekerns/tests synthesis/synthesis tests11:53
zewanHi all. I have a question. What is the maximum clock frequency could get in ASIC?12:14
stekernzewan: not my area of expertise, but that qustion need to be more specifially defined for someone to be able to answer it. at least the following information is missing 1) Maximum clock frequency of what? 2) what ASIC technology are you going to use?12:24
stekernI assume or1200 on 1)12:25
zewan1) or120012:26
zewan2) I thought that this processor has already been implemented in ASIC12:26
stekernyes, there are several companies that has used or1200 in ASICS12:28
zewanso, do you know max freq of those chips?12:30
stekernsamsung is one12:30
stekernthere is another12:31
zewanOk Thanks, but I didn't get the answer. Is there any SoC comparable to ARM Cortex(not fpga)?12:35
stekernyes you got the answer to your question "I thought that this processor has already been implemented in ASIC"12:37
stekernI think the mp3 decoder is running at 100 MHz, not sure how that is interesting, since I have no idea what technology they used in that chip12:38
stekernin return, you didn't answer my question: what ASIC technology are you going to use?12:40
stekernso until you've answered that, I suggest we assume 10 um12:41
stekern1 MHz is probably _very_ optimistic12:42
zewanThank you again. I think the problem in my english ))12:45
zewanI just waiting for answer like: XXX company implement or1200 SoC working on 700MHz12:49
stekernjuliusb: peters mail got me thinking about some cool (long term) mor1kx features15:36
stekernfor a cappuccino without delay slot15:38
stekernsince we have the flag setting decoupled from the branch, it should be relatively easy to do very simple branch prediction by only looking at that15:50
stekernit has really nothing to do with his mail, but the thread of thought started there15:59
stekernsince he probably wants the register output in decode stage to resolve the branches already there16:00
stekernI mean l.jr and l.jalr as well16:02
stekernperhaps we want that too16:03
stekernfor cappuccino16:03
stekernwell, well, one step at a time, something worth investigating in the future16:04
stekernwe are not even resolving branches to immediates in decode stage16:04
stekernor we are, but we are just registering them to execute stage16:05
stekernbaby steps, baby steps... I want to push out my current pipeline changes nice and slowly, with bisectable commits (as you may have noticed)16:06
andresjkpoke53281: very nice work the web-based emulator you did, congrats!19:41
poke53281Only a few weeks of work. First in C, than the port to Javascript.19:48
andresjkoh, it runs very fast for been made in interpreted language. Any future plans for the project?19:53
poke53281Running a C64 emulator running Zork in the framebuffer. Then I have an emulation chain x86->Javascript->MOS6502->ZMachine *g*19:55
poke532812. Include a flash memory for a little bit more space and on demand reading from the webserver.19:56
poke532813. Improve the TLB handling. Maybe rewrite the miss handler in Linux to support multiple ways.19:56
stekerntook a while to grasp what your speaking about, but yeah, very cool stuff poke53281 20:16
poke53281for the other people in the chatroom. I am talking about20:19
_franck_indeed, very cool stuff23:16
@juliusbpoke53281: that is one of the coolest things I've ever seen :)23:37

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