IRC logs for #openrisc Wednesday, 2012-12-05

olofkjuliusb: Hey, I thought I was the coolest thing you've ever seen00:07
olofkok, you said one of the coolest. Fair enough00:08
poke53281Thanks juliusb00:19
@juliusbman, document editing sucks02:52
@juliusbchews up so much time!02:52
stekernjuliusb: how rude of you to not answer within 2 minutes :(05:33
stekernjuliusb: I did a synthesis test on espresso as well, there I actually got a resource _decrease_ by ~1% and fmax increase by ~10%06:55
@juliusbstekern: yep, I know, i'm pretty rude :)11:36
@juliusbstekern: great work with those changes then11:36
@juliusbhave I pulled them in yet?11:36
mor1kx[mor1kx] juliusbaxter pushed 8 new commits to master:
mor1kxmor1kx/master d273ffd Stefan Kristiansson: cappuccino/cpu: whitespace cleanup11:38
mor1kxmor1kx/master 8dcc9fb Stefan Kristiansson: espresso/lsu: whitespace cleanup11:38
mor1kxmor1kx/master 45f83c3 Stefan Kristiansson: lsu: rename alu_result_i to lsu_adr_i11:38
@juliusbok, merged11:38
stekernyup, nice got another set prepared this morning ;)12:01
stekernI think the rest is just cappuccino changes though12:01
stekerna small change in decode to output a branch indication and branch target12:02
stekernI managed to refractor that so most of what I had there is now in ctrl_branch12:03
stekernI think the dsx passing with my pipeline rework branch is just a coincident, it still fails in my for-openrisc branch when I merged in the changes I thought would have fixed that12:04
stekernlooks like it's a branch and an exception that happens at (almost) the same time and the branch target get confused somehow12:04
stekernso I'm going to look a bit more at that to make sure there won't be any bugs lurking around related to that12:05
@juliusbstekern: (DSX fail) is it a confused branch target or a confused EPCR?13:01
@juliusbthis is the thing I noticed13:02
@juliusband was trying to fix13:02
stekernconfused branch target13:02
stekernthe confused EPCR I have fixed13:03
@juliusbit's probably different now, but after the delay slot instruction had completed, and the branch had been indicated to the fetch unit, the control stage forgot it was in a delay slot, and if there's an exception, it sets the EPCR to the delay slot instruction, and should, instead, set it to the branch target13:03
@juliusboh great :)13:03
stekernthat was the failing intloop test13:03
stekernit's not in openrisc/mor1kx yet though, but queued up13:03
stekernthe DSX fail is a bit odd, it has a lsw with misalign in a delay slot to a bf, the bf should branch to test_func, but instead the test_func branch target is confused into being test_fail when the exception comes one cycle after the l.bf13:06
@juliusbya, odd13:07
stekernbut I just ran the test after merging the changes I thought would fix it before 'running' off to work this morning13:08
stekernso haven't looked at it in detail13:08
stekernok, so I think I've figured out the DSX fail and why it's not happening in my pipeline rework18:19
stekernthe sequence is the following: l.sfeq r0,r0; test_func; l.lwz r1,1(r0); test_func: l.jr r918:21
stekernso the exception in the delay_slot (the l.lwz r1,1(r0)) will be generated one cycle after l.jr r9 is in execute18:23
stekernand when l.jr is in execute, it will generate ctrl_branch_occur (so before the exception)18:23
stekernin my pipeline rework I introduced the pipeline bubble on such conditions, to prevent the fetcher from being confused when ctrl/mem stage is stalling a jump18:24
stekernso there it can't happen18:24
stekerni.e. the condition = a jump following a load/store18:25
olofkPlanned downtime20:51
@juliusbolofk: that was quick23:12
@juliusbstekern: very good, what about some overriding signal to make sure that an exception before such instructions-which-reach-forward-in-the-pipeline?23:13
@juliusbi mean something to make sure the exception overrides23:14

Generated by 2.15.2 by Marius Gedminas - find it at!