IRC logs for #openrisc Wednesday, 2012-11-14

@juliusbstekern: I'm just wondering if we really need to split out the SPR units01:03
@juliusbprobably tick timer and PIC unit would make sense01:04
@juliusbthe debug unit is heavily combined with the control unit01:04
@juliusbthat's not going to be uniform across pipelines I suspect01:04
@juliusbOK tick timer is easy to do01:19
@stekernjuliusb: I share your hesitation about SPR's04:48
@stekernthe SPR read/write logic is very pipeline dependent04:49
@stekernwhen I'm done with what I'm doing now, spr reads will be 1-cycle instructions04:50
@stekern_franck_: you can do all those things, and you have full admin rights to openrisc/openOCD, so you should be able to do all you need there too04:53
@stekernbut why would you rename Franck79/openOCD?04:53
@stekernjust put what you have now in a seperate branch04:54
@stekernjuliusb: hmm, am I confused or did you actually have the wb stage in execute as well?06:36
_franck_stekern: you're right, I just don't "think git"08:57
_franck_just created a new branch called next and make it the default branch08:58
@stekernI mostly think like a git ;)09:50
@juliusbstekern: yes, on cappucinno it was basically everything, memory and writeback in execute stage13:50
@juliusbthe when t he execute stage was finished there was nothing left for that instruction to do13:50
@juliusbthe write into the RF occurred on the "execute stage is done" signal cycle13:50
@juliusbstekern: SPR write/read logic waits can be handled with the ACK on the internal SPR bus13:51
@juliusbanyway, last night I got the PIC and TT units in nice little modules,13:51
@juliusbi was playing with cappuccino core13:51
@juliusbi found some bugs :)13:51
@juliusbtrying to fix them13:51
@juliusbmainly the value of EPCR when you get a PIC or TT exception when you're branching13:51
@juliusbi have a nice littlet est I added, or1k-intloop and or1k-tickloop I think13:52
@juliusbit was a test of the prontoespresso "sleep" functionality13:52
@juliusblike, when we get a l.j 0 instruction, I shut down the fetch unit (in pronto)13:52
@juliusbbut, for cappuccino it's failing13:52
@juliusbI found a fix, but it broke other things :-/13:55
@juliusbso, still hacking on it13:55
@stekernso what do you reckon, should I break this stuff I'm working on now as a new pipeline implementation or "upgrade cappuccino"?14:06
@stekerncaffe latte would be the obvious name :)14:06
@stekernI guess it depends how it ends up resource wise14:07
@stekernwhat would the EPCR end up as in the bug you are looking at?14:10
@juliusbstekern: it ends up as the PC of the delay slot I think14:47
@stekernah, I haven't updated mor1kx-devenv in a while16:03
@stekernin a long while it seems :/16:03
@stekernbut that sounds like a good catch16:13
@stekernI just realized that the TRACE stuff probably doesn't work anymore for me17:10
@stekernat least not the register values, since they are not written back at the same time any more17:11
@juliusbdo the trick I put into espresso17:41
@juliusbsnoop the result bus going into the RF module when the RF write signal is high17:41
@juliusbactually, you should probably check the write address, see if that is the one you want, if so snoop that result bus, otherwise read from the RF17:42
@stekernsounds reasonable, I'll have a look when it's starting to remotely to work17:50
@stekernright now I need to wrestle the execute bypass logic into submission17:51
@stekernbut since I now have the alu result registered I should be able to use that instead of the one that is saved in rf17:55
@juliusbhmm, quite probably, yes17:56
@juliusbI was contacted by some Indian guys who put this paper together:
@juliusbout of interest18:35
@juliusbIt's a hot one, Downloads (6 Weeks): 018:35
@juliusbAh this is a direct link to the PDF:
@olofkI haven't got a clue what that abstract is about20:06
@olofkor is it some kind of out-of-order algorithm?20:08
@olofkSeems like they managed to reduce some matrix test time by 30%. That's good20:14
@juliusbsome bit of logic they wacked into the execute stage of the OR120020:30
@stekernvery strange results21:04
@stekernwhat is that dhrystone vs coremark graph supposed to show?21:04
@stekernI'm probably reading table 3 wrong, but to me that looks like worse performance21:08
@stekernand why did they use gcc 3.4.4? (where did they even dig that out?)21:10
@stekernyay, execute bypass works21:25
@stekernnow I just need to handle load->execute21:26
@olofk_franck_, I'm adding your jtag_vpi stuff to orpsocv3 now, but I'm getting Ignoring packet error, continuing... in GDB. Any clues?22:03
@olofkThere's a lot of traffic between openOCD and the jtag tap even when gdb is not connected. Is that normal?22:25
@olofkhmm... no lucj with adb_dbg_if either22:44
_franck_olofk: traffic is normal because openOCD is pulling the debug interface23:16
_franck_did you try to did you try to clone this repo git://
_franck_and try make rtl-tests TEST=or1200-led VCD=1 VPI=1 ?23:18
_franck_then you can test your openOCD /gdb setup23:18
@olofk_franck_: Yeah, I should probably do that first23:43
@olofkI got busy trying to release a stable API for orpsocv3 core descriptions instead23:44

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