IRC logs for #openrisc Thursday, 2012-11-15

@stekernjuliusb: I'm not seeing you doing anything special for get_gpr in espresso?04:32
@stekernI also see that the trace actually snooping the rf_result, but again, espresso isn't doing anything special06:58
@stekernno worries though, I'll figure that out06:59
@stekernthink I've got the get_gpr working so the l.nop reports work06:59
@juliusbstekern: I thought I did do something with both espresso and prontoespresso for get_gpr?! I'll check...11:56
@juliusbbtw, you're up _early_!11:56
@stekernisn't 4:00 a normal time to start your day with a bit of mor1kx pipeline hacking? :)12:37
@stekernI've got lsu rf bypass working, but hooking up rfa_o and rfb_o straight to lsu_result_o made a terrible path :(12:40
@juliusbstekern: I wish!!12:40
@juliusboh, really? A path in from the data bus?12:40
@juliusbthat's a shame12:40
@stekernI've got that covered by the fact that the loads are stalled one extra cycle the way things are at the moment12:41
@stekernso I forge on, have to get back to that later12:41
@stekernlatest synthesis result landed on 90 MHz12:41
@stekernbut that might decrease while fixing stuff :)12:41
@stekernI guess I can just stall one extra cycle on the "corner case" where the loaded register are used right after the load12:42
@stekernright now I'm reworking the spr access12:42
@stekernso it will be handled in mem stage12:43
@stekerni.e. address calculated in execute, result shows up in mem stage, and result is written to reg in wb12:44
@stekern-> 1 cycle mfspr12:44
@juliusball sounds good man13:59
@juliusbstekern: it turns out that I am going to come along to OSHUG tonight14:00
@juliusbI meant that for14:00
@juliusbjeremybennett: it turns out that I am going to come along to OSHUG tonight14:00
@juliusbI'll be a little late though, getting in just after 714:00
@stekernjuliusb: sorry, the "rf snooping" commit was in your latest commits, I thought I had pulled them16:19
@stekernso that's basically what I do now, except it's a bit more complicated, since the gpr writeback can be in execute, ctrl (mem) or wb16:21
@stekernjuliusb: spr access question: the ack logic isn't really implemented, right?16:31
@stekernexcept for du16:32
@juliusbstekern: SPR Ack logic?18:23
@juliusblike, the ACK for the SPR accesses?18:23
@juliusbthe TT and PIC are tied to 1, I can tell you that much :)18:23
@juliusbbut the idea is the SPR unit may not ack immediately18:23
@juliusbthey may not all be single cycle access18:23
@juliusbso is there a thing in git where if you check out a remote branch and then work on it without branching it locally, and then go branch -a it will says (no branch)?20:28
@stekernjuliusb: all are tied to 1, if they wouldn't be reading them wouldn't work (at least not in cappuccino), since the ack is not read anywhere20:44
@stekernit's fine though, I'm thinking about threating them as any 'alu-instruction'20:46
@stekernwell, not exactly, it's gonna stall from ctrl/mem stage if ack isnt asserted20:53
@stekernfor now I'll just continue to assume that ack is tied to 1 though20:54
@stekernre the git thing, not quite sure what you are after?20:56
* ams waves.23:38

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