IRC logs for #openrisc Friday, 2012-03-02

derRichardjonibo: ping00:54
derRichardi think i've found a serious vm bug in linux openrisc.00:54
Lampus|2It's again me with my problems =)12:49
Lampus|2stekern: Sorry for disturbing you again, but I'm need some help. Can you look at this log of adv_jtag_debug , please?12:57
Lampus|2Now I'm using LEGACY_DBG_IF with GENERIC_JTAG_TAP12:57
Lampus|2adv_jtag_bridge was recompiled with SUPPORT_LEGACY=true12:58
Lampus|2Why it can't find DEBUG command?12:59
Lampus|2Exteranal Altera USB Blaster is used13:00
stekernhooked up to what?13:00
stekernsome gpios of the fpga?13:00
stekernis that known to work?13:01
Lampus|2Yes, I have used this pins before for some debug signals output13:01
Lampus|2But adv_jtag_bridge correctly recognize ID Code13:02
stekernI meant, is it known to work with adv_jtag_bridge, LEGACY_DBG_IF and GENERIC_JTAG_TAP?13:02
stekernand are you using the "legacy" debug if in the fpga?13:04
Lampus|2stekern: But you have used GENERIC_JTAG_TAP with LEGACY_DBG_IF for de0-nano. What I can use instead?13:05
Lampus|2Yes, In fpga legacy debug is enabled13:05
Lampus|2*instead adv_jtag_bridge i mean13:06
stekernI have used it with a ftdi based external debugger and or_debug_proxy and openocd13:23
stekernI'm not saying that your setup shouldn't work though13:24
Lampus|2Thank you for direction13:24
stekernopenocd should have support for usb-blaster afaik13:24
Lampus|2It works fine with adv_jtag_if and altera_jtag_tap, but only with disabled CRC checking in adv_jtag_bridge13:26
Lampus|2And breakpoints don't works properly with such configuration13:27
Lampus|2stekern: And one more question. In what state should be my port for DE0 for merging in upstream?13:28
stekernI'd say it should pass the make rtl-tests simulation and tested on the FPGA13:31
Lampus|2About tests... For some reasons make rtl-tests for de0-nano need vlib from MultiSim13:32
Lampus|2But as I know it must works properly with iverilog (Icarus Verilog) too13:33
Lampus|2One second...13:34
stekernwell, if you get it to run with icarus, that's great13:35
Lampus|2make[2]: Leaving directory `/home/lampus/Projects/FPGA/orpsoc/sw/tests/or1200/sim'13:35
Lampus|2/bin/sh: vlib: command not found13:35
Lampus|2make rtl-tests from orpsoc/sim/run directory works fine with iverilog13:36
derRichardjonibo: sorry about the mailinglist confusion. joe and i had a discussion about moderated lists and i thought is a black hole23:09

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