| --- Log opened Thu Sep 13 00:00:26 2018 | ||
| @juliusb | wb__: DCR errors? | 02:15 |
|---|---|---|
| @juliusb | wb__: have you tried singel register reads and writes to somewhere on the bus (the SRAM again) | 02:15 |
| -!- [X-Scale] is now known as X-Scale | 05:44 | |
| wb__ | When I try to connect from gdb I get a timeout error and in the jtag_bridge I get a crc error | 10:29 |
| wb__ | from gdb (gdb) set remotetimeout 10 (gdb) target remote:9999 Remote debugging using :9999 Remote communication error. Target disconnected.: Connection reset by peer. | 10:30 |
| wb__ | I can watch the jtag and debug signals on the FPGA using chipscope, just hard for me to see a full jtag transmission as chipscope is pretty narrow on what it records. | 10:32 |
| wb__ | I was feeling pretty good when I saw the memory read and write data from the test mode show up on the wishbone bus, but I don't why it wont complete the test mode and just stalls at starting the cpu. | 10:33 |
| wb__ | I have a bus blaster from dangerous prototypes, Can I use that with adv_debug_sys over the xilinx usb cable? | 13:50 |
| wb__ | ok using the bus blaster I think I'm connected, but using openocd i'm now getting an error when I try to reset the cpu | 16:51 |
| wb__ | I just loaded a program using the busblaster, only a few issues, I have seen a few "Error: Memory write failure!" | 17:35 |
| wb__ | Also I can't halt or reset the cpu, when I do I run into a core dump with openocd | 17:37 |
| wb__ | Error: or1k_assert_reset: implement me | 17:37 |
| wb__ | Error: or1k_deassert_reset: implement me | 17:38 |
| wb__ | openocd: driver.c:191: interface_jtag_add_dr_scan: Assertion `field == out_fields + scan->num_fields' failed. | 17:38 |
| wb__ | Aborted (core dumped) | 17:38 |
| wb__ | Overall I can probably get what I need imediatly done using the busblaster, not sure why the xilinx usb cable is being such a pain but I'd like to figure out the other errors with the bus blaster | 17:39 |
| @juliusb | what's the difference between test mode and standard mode? | 19:58 |
| @juliusb | clock frequency or something? | 19:59 |
| -!- Netsplit *.net <-> *.split quits: LoneTech | 23:02 | |
| -!- Netsplit over, joins: LoneTech | 23:03 | |
| --- Log closed Fri Sep 14 00:00:27 2018 | ||
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