| --- Log opened Wed Sep 12 00:00:24 2018 | ||
| wb__ | Hello, I'm having issues getting the debug port working on the openrisc. I'm at a point where I'm sure the jtag is working and can run the adv_jtag_bridge in test mode and read the SRAM, but I am stalling on "Starting CPU0!" | 20:06 |
|---|---|---|
| wb__ | When I run the adv_jtag_bridge not in test mode I get DCR errors with burst read timed out. | 20:17 |
| --- Log closed Thu Sep 13 00:00:26 2018 | ||
Generated by irclog2html.py 2.15.2 by Marius Gedminas - find it at mg.pov.lt!