IRC logs for #openrisc Wednesday, 2017-04-12

--- Log opened Wed Apr 12 00:00:26 2017
wallentoshorne: we interface it to our trace debug infrastructure at Open SoC Debug02:19
wallentowhich essentially puts it into packets with PCs and timestamp and on the host we reconstruct the function call flow02:20
wallentoits on my todo list to build an example which doesn't need optimsoc02:20
wallentoand mithro's soc02:20
mithrohey wallento02:21
mithrowallento: Turns out that I can do a GSoC project in about 2 weeks :-P02:22
wallentothats great :)02:23
wallentowhich board do you target again?02:23
mithroBut I've been regularly working with Digilent Atlys, Numato Opsis and Numato MimasV2 recently02:24
mithroJust been adding Digilent Arty support02:24
mor1kx[mor1kx] wallento pushed 1 new commit to master:
mor1kxmor1kx/master d73be37 Stefan Wallentowitz: Merge pull request #50 from openrisc/traceexec-jump...02:24
wallentoexcellent, maybe we can collaborate on the arty then, because its the only one I have at hand02:24
wallentoas a ramp up02:25
mithroWe have some support for the Pipistrello and minispartan602:25
mithroOh and the Nexys Video02:25
wallentoa guy at philipp's group currently finishes the gdb<->opensocdebug<->adv_dbg_sys stuff02:25
wallentoI meant to get one of the Nexys4 video02:26
mithrowallento: Probably will add Genesys(?sp) 4 support too02:26
mithroAny Spartan 6 / Artix 7 / Kintex 7 board with DDR and video inputs/outputs makes a good target for us02:27
mithroFor anyone who is interested in Linux on our SoC (which is also Linux on or1k for now) -- feel free to join!forum/linux-litex03:56
mor1kx[mor1kx] wallento deleted traceexec-jump at 1dea99f:
mor1kx[mor1kx] wallento created fixes (+8 new commits):^...d9a7ea5be95704:13
mor1kxmor1kx/fixes 978d2d2 Olof Kindgren: Fix width mismatch in store buffer04:13
mor1kxmor1kx/fixes 4ecbb64 Olof Kindgren: Fix unused wires in lsu cappucino04:13
mor1kxmor1kx/fixes 4bd9ba7 Olof Kindgren: Fix unused/missing wires in mor1kx_fetch_cappuccino04:13
mor1kx[mor1kx] wallento pushed 1 new commit to fixes:
mor1kxmor1kx/fixes a12eed1 Stefan Wallentowitz: Add travis lint04:24
mor1kx[mor1kx] wallento force-pushed fixes from a12eed1 to 16ecf91:
mor1kxmor1kx/fixes 16ecf91 Stefan Wallentowitz: Add travis lint04:48
bandvigHello all. Currently we keep ability of asynchronous reset for CPU core, while Wishbone specification, for example, requires synchronous reset.07:18
bandvigIf I understand correctly, removing asynch-reset makes possible to reduce hierarchy in many registers by converting07:18
bandvig“if (rst) begin <operators> end else if (pipeline_flush) begin <same operators> end …” to “if (rst | pipeline_flush) begin <operators> end …”.07:18
bandvigI see one risk for simulation here. If pipeline_flush is output of combinatory logic, its initial value ‘X’ could block initial reset and simulation could fail.07:19
bandvigTo overcome this initial values are required for all pipeline_flush contributors.07:19
bandvigHowever it is not a problem at least for MAROCCHINO pipe, because pipeline_flush is a register there.07:19
bandvigSo, is it really useful to keep asynchronous reset for CPU core?07:19
mithroSo, what is the best way to build an initrd for or1k?07:46
bandvigRe-formulation: is there a strong reason to keep asynchronous reset ability for CPU core?08:17
mor1kx[mor1kx] wallento pushed 9 new commits to fixes:
mor1kxmor1kx/fixes ac44868 Stefan Wallentowitz: Minor style fix08:22
mor1kxmor1kx/fixes 5fb65c4 Stefan Wallentowitz: Replace delayed assignments in unclocked blocks08:22
mor1kxmor1kx/fixes 8f1da6f Stefan Wallentowitz: Fix linter warning for incorrect SPR select bits...08:22
mor1kx[mor1kx] wallento opened pull request #51: Linter fixes (master...fixes)
mor1kx[mor1kx] wallento pushed 3 new commits to fixes:
mor1kxmor1kx/fixes 80b58b3 Stefan Wallentowitz: Fix register access widths for shadow registers10:01
mor1kxmor1kx/fixes c58d29e Stefan Wallentowitz: Fix MMU way indexing10:01
mor1kxmor1kx/fixes 32fa112 Stefan Wallentowitz: Fix higher address bis in MMU translation10:01
-!- andrzejr_ is now known as andrzejr17:00
shorneHi all, I have put together this project to capture all of the files that are currenting in openrisc repo's that will not really go upstream in the end19:47
shornei.e. the initramfs directory in linux19:47
shorneor the site.exp in or1k-src (the old gcc, gdb and binutils project)19:48
mithroshorne: So do you have real or1k hardware? Or are you just running on FPGAs like us?22:25
shornemithro: I'm very low budget with a de0 nano only23:36
shorneI might get something else, but I got de0 nano to force me to design my own hardware23:36
mithroshorne: I wonder how the de0 nano compares to the MimasV223:39
shornenice, that does look to have everything I would need23:44
shornemithro: I mean everything anyone would who is starting out, its xilinx23:45
shornedo you know what the stereo jack is connected to?23:46
mithroshorne: the lx9 is a bit small - it would have been nice if they had a lx25 option23:50
--- Log closed Thu Apr 13 00:00:28 2017

Generated by 2.15.2 by Marius Gedminas - find it at!