IRC logs for #openrisc Thursday, 2017-04-06

--- Log opened Thu Apr 06 00:00:17 2017
wallentomithro, shorne is in Japan01:49
mithrowallento: Must just keep strange hours :-P01:49
wallentoyeah, late at night I think01:53
mithrowallento: We didn't get any bites on the opendebugsoc stuff :-(02:41
wallentomithro, yes, sorry, I was a bit snowed recently02:45
wallentonow I will have some more free time and will have a look at it again02:45
wallentoI think it was not suited as a GSoC due to the state of things and actually it was not so complex02:46
wallentoI propose I will pick it up the next two weeks on the mailing list, get the uncommitted features from philipp and then do it myself and/or together with you02:46
wallentounfortunately the open soc debug topics didn't attract students in GSoC at all02:46
mithrowallento: I'm happy to work together on it with you02:47
wallentoI am following your stuff for a while now but didn't get hands on it, great chance now :)02:48
mithrowallento: It's actually gotten less critical to have now that we have some basic qemu emulation of the SoC going02:49
wallentoyeah, I read it, this sounds great02:49
wallentoas philipp said, open soc debug is currently focused on tracing, integrating it together with run control debug in your soc should also help us generalizing our approaches02:50
wallentogtg, I will followup soon02:50
mithrowallento: It was surprisingly easy to do the hardware emulation stuff -- the hardest part is turning bit banging stuff back into register accesses that qemu uses02:50
shornemithro: yes, in japan.  During the week I can only login after work and after my kids go to sleep03:11
shorneRight now I just logged in via my phone to double check some things03:11
mithroshorne: fair enough, if your around in the evening sometime try pinging me03:12
shorneok, usually its betwen 10 and 12 pm Japan time.  Ill let you know03:12
shorneI checked your device tree, it looks ok but not sure about other things03:13
shornei.e. what does your memory mapp look like for the SoC? do you have the source for it?03:13
shornei.e. is serial really at address 0x900000003:13
shorneAlso, how do you load the OS?  via openocd? i.e. load_image?03:14
shorneor are you doing via bootloader03:14
mithroshorne: I'm currently using qemu - I haven't yet tried loading the kernel I built03:17
mithroshorne: The memory map is just DDR starting at 0x4000000 and 64Megabytes big03:18
mithroshorne: Our UART isn't compatible with the one used by or1ksim / stock or1k03:19
shorneright, but that should just be a change to the device tree03:20
shorneuse , compatible=<myuart,driver...>03:20
shorneis your qemu stuff in a repo?03:21
mithroOr if you prefer ld script -
mithroshorne: Not upstream yet -still very hacking, but you can find it at
shornecool, if its or1k then I dont need another toolchain03:22
mithroshorne: Use the "" script to get the qmu built03:22
mithroshorne: We support both lm32 and the or1k at the moment03:22
shorneI can give it a shot afterwork, I cant open links of this device now03:22
mithroI can email you the details if you want03:23
mithroshorne: Our UART is super simple, it's basically a FIFO with full/empy flags03:23
shornesure, you should have my details?03:23
shorneIll get back to work now03:25
mithroshorne: I don't seem to?03:25
mithroAhh found your email via Google :-)03:26
shornemithro: thanks, I got the mail11:28
shornewbx: did you see my patch for qemu shutdown?16:59
mithroshorne: I'll probably be around most of this weekend. If you have time available, I'm definitely happy to work around your schedule.22:53
--- Log closed Fri Apr 07 00:00:18 2017

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