IRC logs for #openrisc Monday, 2017-04-03

--- Log opened Mon Apr 03 00:00:12 2017
olofk_webshorne_: Thanks for the fixes to adv_debug_sys03:12
olofk_webJust a comment though, after checking the IRC back logs03:12
olofk_webThe way to set a custom define for a system building with Quartus is to add a TCL file that uses the Altera syntax to set it03:13
olofk_webThen you add the file to a fileset and set file_type=tclSource (and it's recommended also to set usage = quartus)03:13
olofk_webThat way FuseSoC will source the tcl file when creating the Quartus project file03:13
olofk_webBut it should also be possible to set this on the command-line. Some backends support this now, but not quartus yet. I'll fix that03:14
olofk_webSo, doing it the TCL way is more for static values that you don't want to change between builds. Doing it with a CLI option is more useful when you want to change things easy at build time03:15
olofk_webThe syntax for setting a verilog define in quartus is set_global_assignment -name VERILOG_MACRO "$KEY=$VALUE"03:16
olofk_webFor your $KEY/$VALUE03:16
olofk_webshorne_: Pushed a patch now to handle setting defines from CLI with quartus now03:51
olofk_webIt requires you to define a parameter section for each define03:51
shorne_olofk_web: thanks. I wanted to use for adv_debug_sys, but I think using parameters on the verilog modules makes more sense here06:34
olofk_webshorne_: Definitely. I've been trying to get rid of defines when possible. Cleaned up a few of the old cores from OpenCores06:39
olofk_webBut it can be good to know if you need to set a define at some point06:40
shorne_olofk_web: yeah, I will have something to reference next time.07:31
-!- shorne_ is now known as shorne07:31
shorneolofk_web: I never really got into the tcl scripting stuff before.  (though I would like to... since it seems a lot of rtl workflow centers around that)07:33
shornebut lately I am hacking on openocd which has "jim tcl"  at its core07:33
shorneits pretty basic actually07:33
olofk_webOh god! STAY AWAY FROM TCL!!!!!!!07:54
olofk_webIt's an absolute crap language for these sort of things. It's a complete mystery how it ended up being the preferred EDA scripting language. It's so bad, that most solutions seem to generate TCL from some other language nowadays07:55
olofk_webBut otoh, as usual, it's the tool that's available if we wnat to work on EDA, so I guess it makes sense to know it07:56
olofk_webJust saying that you "would like to" know TCL only comes from a person who hasn't experienced it enough yet :)07:56
olofk_webHmm...any good advice on a verilog construct that forces synthesis/simulator to exit?08:01
olofk_webI want to break when an invalid parameter value is found08:02
olofk_webFor sim, I can use $finish, but that doesn't help for synthesis08:02
olofk_webI've used $error, but I realize now that this is really a SystemVerilog keyword, so not supported by some tools08:02
olofk_webThis is what it looks like today =>  initial if(FIFO_AW == 0) $error("%m : Error: FIFO_AW must be > 0");08:03
ZipCPUHow about a different approach: localparam LCL_FIFO_AW = (FIFO_AW < 2) ? 2 : FIFO_AW; ?08:11
olofk_webGood idea. I could still display a warning that it's set to minimum allowed08:21
shorneolofk_web: good to know I should avoid tcl... fusesoc works well enough for me now anyway09:12
olofk_webTime to run10:11
mafmany gsoc candidates to port GCC from scratch? :)15:03
shornefyi, I posted openrisc multicore patches here for openocd17:21
shorneneed to make it support "smp" (meaning reset,halt etc happen on all cores not just one)17:22
--- Log closed Tue Apr 04 00:00:14 2017

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