| --- Log opened Wed Mar 22 00:00:54 2017 | ||
| mithro | Does anyone know the status of or1k support in qemu? | 08:21 |
|---|---|---|
| promach | is it possible to separate the pfpu32_muldiv.v signals from mor1kx_execute_alu.v ? I mean purely for testing only | 10:55 |
| bandvig | promach: please find my test-bench for FPU modules in https://www.pastiebin.com/58d2b87e4e08d | 13:53 |
| bandvig | promach: by the way last time I tested division. To use the test bench you have to include in simulation both FPU: original OR1200 from folder verilog/fpu (it plays role of reference) and for CAPPUCCINO FPU from folder verilog/pfpu32 | 13:53 |
| bandvig | and don't forget to add rtl/verilog folder in include paths: mor1kx-defines.v and mor1kx-sprs.v are required | 13:56 |
| ZipCPU | bandvig: promach is offline now. He's usually only on during the daylight hours in Singapore. I'll be happy to relay your answer, though, when he gets back on. | 13:57 |
| bandvig | ZipCPU: well, and I hope he reads julius' log | 13:59 |
| ZipCPU | Thanks for reminding me! I had forgotten. | 13:59 |
| bandvig | promach: one more note. The test-bench doesn't contain "stop simulation" criteria because I run it in ISim for finite number of nanoseconds. | 14:06 |
| bandvig | promach: can I ask for which purpose you are going to simulate mul/div? | 14:19 |
| --- Log closed Thu Mar 23 00:00:55 2017 | ||
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