| --- Log opened Fri Mar 17 00:00:46 2017 | ||
| shorne | spam time, finally pulled the trigger on gdb patches again | 01:44 |
|---|---|---|
| wallento | shorne: awesome | 03:42 |
| wallento | mithro: It is done but I didn't test it, I will have to ask philipp again | 03:43 |
| wallento | a student of him did it | 03:43 |
| wallento | the run control (gdbserver) stuff | 03:43 |
| mithro | wallento: So, how would I pull it into an existing verilog based design? | 03:43 |
| wallento | You will need to assign an IO to it, commonly UART or JTAG | 03:44 |
| wallento | then its kind of orthogonal, just a different subsystem | 03:45 |
| wallento | I can point that out in your code | 03:45 |
| wallento | the interface to your soc is the debug unit interface of mor1kx | 03:45 |
| wallento | and potentially your reset signals (CPU and system) | 03:45 |
| wallento | because you can use the SCM (System Control Unit) to control those | 03:46 |
| mithro | So, I assume I just need to connect the UART to a set of pins and the debug unit to my mor1k | 03:47 |
| wallento | mithro: yep | 04:40 |
| mithro | wallento: How do I get the verilog code? | 04:41 |
| wallento | let me get back to the mailing list and ask philipp | 04:42 |
| wallento | it is supposed to be here, but I cannot find it in any public branch https://github.com/opensocdebug/hardware/tree/master/modules/cdm_ads | 04:43 |
| mithro | I was poking around https://github.com/opensocdebug/demo_testbench | 04:43 |
| --- Log closed Sat Mar 18 00:00:48 2017 | ||
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