IRC logs for #openrisc Friday, 2017-03-17

--- Log opened Fri Mar 17 00:00:46 2017
shornespam time, finally pulled the trigger on gdb patches again01:44
wallentoshorne: awesome03:42
wallentomithro: It is done but I didn't test it, I will have to ask philipp again03:43
wallentoa student of him did it03:43
wallentothe run control (gdbserver) stuff03:43
mithrowallento: So, how would I pull it into an existing verilog based design?03:43
wallentoYou will need to assign an IO to it, commonly UART or JTAG03:44
wallentothen its kind of orthogonal, just a different subsystem03:45
wallentoI can point that out in your code03:45
wallentothe interface to your soc is the debug unit interface of mor1kx03:45
wallentoand potentially your reset signals (CPU and system)03:45
wallentobecause you can use the SCM (System Control Unit) to control those03:46
mithroSo, I assume I just need to connect the UART to a set of pins and the debug unit to my mor1k03:47
wallentomithro: yep04:40
mithrowallento: How do I get the verilog code?04:41
wallentolet me get back to the mailing list and ask philipp04:42
wallentoit is supposed to be here, but I cannot find it in any public branch
mithroI was poking around
--- Log closed Sat Mar 18 00:00:48 2017

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