IRC logs for #openrisc Tuesday, 2017-03-07

--- Log opened Tue Mar 07 00:00:31 2017
stekernolofk: looking at the fetch refill code, it does indeed lack handling of err01:06
stekernbut I don't think it is as complicated to fix as you make out01:06
stekernthe cache line get invalidated on the first write, so if the refill in the middle, the cache line will remain invalid01:08
stekern*so if the refill aborts in the middle01:08
stekernif the refill aborts on the first access in the cache line, the old data will remain (which is valid)01:09
olofkstekern: ok, but is it enough to just leave the state in the fetch unit to abort the refill, or do we need to sync this to icache too?06:54
stekernafaict, icache should be able to handle it07:16
stekernand the fetcher itself too07:17
stekernit's just that the refill fsm get stuck07:17
stekernunless I am missing something07:17
bandvigolofk: stekern: I do not remember exactly CAPPUCCINO implementation, but in MAROCCHINO I have implemented the following:08:10
bandvigIf IBUS error occurs during re-fill, ICAHCE line keep invalid, IBUS FSM drops transaction, IFETCH generates IBUS error exception.08:10
bandvigolofk: What are the or1k-tests you are talking about? I would like to run it on MAROCCHINO pipeline.08:11
shornebandvig: I am working on one think in the gdb sim for fpu... the ld.rem.* instructions09:18
shorneI dont see that its ever been implemented09:19
shorneDo you have any plan to implement in hardware?09:19
bandvigshorne: You are right, lf.rem.s(d) are  not implemented. And same to lf.madd.s(d).09:32
bandvigshorne: I’m not going to implement them at least in the near future. Perhaps, sometime later.09:32
olofkAs I'm always seem to miss bandvig when he's around, please tell me that the or1k-tests can be found at
--- Log closed Wed Mar 08 00:00:33 2017

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