| --- Log opened Tue Mar 07 00:00:31 2017 | ||
| stekern | olofk: looking at the fetch refill code, it does indeed lack handling of err | 01:06 |
|---|---|---|
| stekern | but I don't think it is as complicated to fix as you make out | 01:06 |
| stekern | the cache line get invalidated on the first write, so if the refill in the middle, the cache line will remain invalid | 01:08 |
| stekern | *so if the refill aborts in the middle | 01:08 |
| stekern | if the refill aborts on the first access in the cache line, the old data will remain (which is valid) | 01:09 |
| olofk | stekern: ok, but is it enough to just leave the state in the fetch unit to abort the refill, or do we need to sync this to icache too? | 06:54 |
| stekern | afaict, icache should be able to handle it | 07:16 |
| stekern | and the fetcher itself too | 07:17 |
| stekern | it's just that the refill fsm get stuck | 07:17 |
| stekern | unless I am missing something | 07:17 |
| bandvig | olofk: stekern: I do not remember exactly CAPPUCCINO implementation, but in MAROCCHINO I have implemented the following: | 08:10 |
| bandvig | If IBUS error occurs during re-fill, ICAHCE line keep invalid, IBUS FSM drops transaction, IFETCH generates IBUS error exception. | 08:10 |
| bandvig | olofk: What are the or1k-tests you are talking about? I would like to run it on MAROCCHINO pipeline. | 08:11 |
| shorne | bandvig: I am working on one think in the gdb sim for fpu... the ld.rem.* instructions | 09:18 |
| shorne | I dont see that its ever been implemented | 09:19 |
| shorne | Do you have any plan to implement in hardware? | 09:19 |
| bandvig | shorne: You are right, lf.rem.s(d) are not implemented. And same to lf.madd.s(d). | 09:32 |
| bandvig | shorne: I’m not going to implement them at least in the near future. Perhaps, sometime later. | 09:32 |
| olofk | As I'm always seem to miss bandvig when he's around, please tell me that the or1k-tests can be found at https://github.com/openrisc/or1k-tests | 18:00 |
| --- Log closed Wed Mar 08 00:00:33 2017 | ||
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