| --- Log opened Tue Dec 27 00:00:46 2016 | ||
| mithro | kc5tja: sorry to hear that :-( | 04:20 |
|---|---|---|
| kc5tja | mithro: Yeah, it sucked. Hit right on Christmas day too. | 11:59 |
| olofk_ | mithro: Not at 33c3, but have some experience with adv_debug_sys | 17:38 |
| olofk_ | Just added a patch to it a few days ago | 17:38 |
| olofk_ | It's quite well-documented also | 17:38 |
| mithro | olofk_: So, I have a uart<->wishbone and ethernet<->wishbone bridges - I can write anything on the wishbone bus, I would like to control the debug functionality in our cpus (like the mor1k) and trying to figure out how to interface this with maybe adv_debug_sys rather than using jtag... | 17:39 |
| olofk_ | Out of curiosity, are you using etherbone? | 17:40 |
| mithro | olofk_: yes, I think we are compatible with etherbone but I believe it's _florent_'s reimplementation | 17:42 |
| olofk_ | What do you mean with "rather than using jtag"? The normal setup is pc client (e.g. openocd) <-> jtag <-> jtag tap (e.g. jtag_tap or xilinx_bscan or altera_virtual_jtag) <-> adv_debug_sys <-> Wishbone/mor1kx | 17:43 |
| mithro | This is on litex+liteeth | 17:43 |
| mithro | olofk_: I was thinking something like pc client <-> wishbone bridge <-> wishbone <-> adv_debug_sys <-> mor1kx | 17:44 |
| olofk_ | There are probably a few ways to do this, some of them likely horribly complicated :) | 17:48 |
| olofk_ | adv_debug_sys is controlled by the tap interface (example here https://github.com/openrisc/orpsoc-cores/blob/master/systems/de0_nano/rtl/verilog/orpsoc_top.v#L434) | 17:49 |
| mithro | olofk_: I can connect them to csr registers on the wishbone bus, but I would really like to do more than one bit at a time | 17:53 |
| olofk_ | So one way could be to use Franck Jullien's jtag_vpi interface to serialize the commands into a byte stream. Then you could do pc <-> (byte_stream_to_jtag_bridge) <-> jtag_tap <-> adv_debug_sys | 17:53 |
| olofk_ | But it would likely be a lot less efficent than what you have today | 17:53 |
| olofk_ | or maybe not actually, since you could run the fake jtag clock quite high | 17:54 |
| olofk_ | The other way would probably be to bypass adv_debug_sys entirely (or reuse the parts facing the CPU) | 17:55 |
| olofk_ | The interface towards the CPU is wishbone-like | 17:56 |
| mithro | olofk_: I would like to reuse as much as possible for the lm32 and the clifford's pico-risc-v thing too | 18:22 |
| olofk_ | mithro: The pulp guys reused adv_debug_sys for their risc-v core called ri5cy. That could be a starting point | 18:24 |
| olofk_ | I guess they still use jtag on the controlling side though | 18:24 |
| olofk_ | And yes, since you asked, of course, it's already packaged for FuseSoC :) | 18:25 |
| olofk_ | https://github.com/pulp-platform/adv_dbg_if | 18:26 |
| --- Log closed Wed Dec 28 00:00:47 2016 | ||
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