IRC logs for #openrisc Friday, 2016-12-02

--- Log opened Fri Dec 02 00:00:09 2016
shorne_Interesting talk about embedded system testing with Fuego00:15
shorne_oleg-nenashev: Fuego uses jenkins, it might be of interest00:16
-!- shorne_ is now known as shorne00:16
shornewallento: I actually am getting 2 more signatures today after I gave this talk today08:54
wallentowe really get this going! :)08:54
shornesupposedly if I have 3 I can get a account08:55
olofk_shorne: Cool. I forgot where you gave the talk. Do you have a link?09:06
shorneits an embedded linux micro conference09:08
shorneuploaded my slides here, similar what I gave at orconf, but more intro to openrisc09:09
shorneMany talks were all in Japanese, but it was interesting09:09
shorneone talk was about sony's use of NuttX in its smaller appliances09:10
shornelike audio recorders09:10
shorneBut, most of sony's products, like cameras, are linux09:12
shorneit seems everything for the companies there was "arm" though (sony, toshiba, fujitsu,)09:13
olofk_shorne: Did you remember to speak slowly without any complicated expressions, as stated on the page? :)09:24
olofk_Cool. I see you did a page on FuseSoC!09:26
shorneolofk_: yes and yes, I thought I I was going to sell people on opencores, the main benefit is inter-operability. Fusesoc is a bit help here.17:56
shornewell librecores (open ip cores) + openrisc platform17:57
shorneand just one of the benefits in inter-opability17:57
ZipCPUHello!  I was wondering if anyone had any statistics on how easy/difficult it was to switch from user to kernel mode as a result of a system call within Linux.20:53
ZipCPUI'm trying to build something similar, and I'm getting disappointed at the complexity of the task.20:53
kc5tjaThat would depend on the CPU in question, I'd imagine.  RISC-V makes this transition nearly instantaneous.20:56
kc5tja(at least, the ISA enables implementations which are very fast.)20:57
ZipCPUHmm ... I'm struggling to see how that is so.  It seems to me that no matter how instantaneous the hardware makes it (and I could be wrong here), you have to pay for it sooner or later.20:57
ZipCPUFor example, if the hardware just switches register sets from user to kernel, then on a full context switch you have to save twice as many registers--right?20:58
ZipCPUFurther, wouldn't you then need to use some special machine instructions to get access to those shadow/special purpose registers?20:58
kc5tjaWell, yes, "nearly" is the qualifier here.  You do have to save and restore state.20:59
kc5tjaKernel-mode is, in practice, used to basically emulate a completely separate processor operating in its own address space.20:59
ZipCPUWell, okay, ... so how does RISC-V make this process simpler?20:59
kc5tjaThere's a CSR (sscratch) which is typically used to point to the current user-mode thread's context area.21:01
kc5tjaOn entry to the trap, you can save registers into this area by swapping sscratch with a register and using SW/SD instructions.21:01
kc5tjaLikewise, when restoring context, you do the reverse.21:02
kc5tjaThe code sequence is large, but it's much cleaner a design than Intel's Task State Segments.21:02
kc5tjaAlso, the trap handler doesn't have to save the entire CPU state if it knows it can get away with not doing so.21:02
ZipCPUIs this documented in volume 1 of the RISC-V ISA?21:03
kc5tjaIn the privilege ISA spec.21:03
ZipCPUSo ... not volume 1?21:03
kc5tjaCall it volume 2 if you like, sure.21:03
ZipCPUOk.  That's the spec I don't have (yet).21:03
kc5tja will have the latest version available.21:07
kc5tjaIt's not ratified yet, as some things are still being discussed.21:08
ZipCPUNot ratified, and already past version 1.0?  Ok ...21:08
kc5tjaBut after 1.10, it will be decreed that all future revisions must be backward compatible.21:08
kc5tjaYeah, they version things weirdly.  2.0 is their ratification version.21:08
ZipCPUOk, I'm pulling it up now.  CSR you say?  Let's see how a search does with that.21:10
ZipCPU"The standard RISC-V ISA sets aside a 12-bit encoding space for up to 4,096 CSRs".  Yeah, I knew there was a reason for building the ZipCPU.  ;P21:11
ZipCPUOk, Tbl 2.3 lists sstatus as CSR #0x100.21:12
ZipCPUkc5tja: Did you deal with *all* of these CSRs with kestrel?21:13
kc5tjaNo.  I have only 18 CSRs (and once I switch to a user-mode-only design, the number will drop).21:16
kc5tjaCSR instructions which reference unsupported addresses are required to perform an illegal instruction trap.21:16
ZipCPUSo, here was the siren call I noticed: It was costing me ~100 instructions for just one part of a trap/syscall, and these instructions are also heavy on memory too.  If you assume that the entire trap takes 200 clocks, then what does that mean for a21:18
ZipCPUserial port which has a new value every 800 clocks or so?21:18
ZipCPUread(serial_fd, &ch, 1) would *never* be able to keep up!21:19
kc5tjaThat's correct.21:22
kc5tjaThat's why Unix(-like) OSes accept a buffer and a length pair; it gives them the flexibility to busy-wait on serial ports until the required number of bytes are sent or received.21:23
kc5tjaSingle-character I/O primitives, like what you find on most 8-bit OSes, just can't keep up with that because the days of 300 bd serial links are long since gone.  :)21:23
kc5tjaIBM mainframes go even further: a system call like read() is translated into a "channel program", a complete set of I/O primitives to be executed by a dedicated I/O coprocessor.21:24
ZipCPUSo ... how would a C-library implement a getchar() system call then?  By polling to wait for something to read, and then issuing a non-blocking read to fill as much of its buffer as is available?21:28
ZipCPUHmm ... maybe I should look that one up.21:28
kc5tjaIs this a multitasking or single-tasking operating system?21:31
kc5tjaIf single-tasking, you can just have a system call that busy-waits.21:32
kc5tjaIf multitasking, it'll be better to suspend the task on a "waiting" list of some kind, and have the serial port's interrupt handler wake the task later.21:32
kc5tjaThat way, the CPU is free to process other things while the task suspends until a character has arrived.21:33
ZipCPUI've actually got some fairly simple code for a pipe, implemented as a FIFO in memory, that can handle the suspension you are describing.  It's nice: I can read/write from interrupt context, and handle the rest21:34
ZipCPUas necessary from a non-interrupt context.21:34
* kc5tja implements something similar in the KIA for the PS/2 port. I needed this because the Kestrel-2 does _not_ have interrupts. ;)21:34
kc5tja(Kestrel-3 does.  But I still want that FIFO.  Progress!)21:35
ZipCPUAnd here I was thinking of implementing a printf as a series of putchar statements as each character became available.  Imagine the waste if every one of those was an expensive trap!21:39
kc5tjaYep.  select() to indicate if a readable channel has data that can be read (and suspend task until this condition is met), then bulk-read what is there with a single read() call.21:40
kc5tjaGetting right pissed.  I now know that my missing characters from my keyboard is definitely **NOT** hardware induced.21:41
ZipCPUYou beat me to it ... I'm still searching the glibc code ... ;)21:41
kc5tjaLag to my cloud server is highly variable, and it's bloody dropping packets.21:41
ZipCPUNo wonder I can't find it ... I was searching stdlib, not stdio ...21:42
kc5tjaThis is, in part, why Unix-type OSes are so shitty at (hard-)real-time applications like user interfaces.21:42
--- Log closed Sat Dec 03 00:00:10 2016

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