IRC logs for #openrisc Sunday, 2016-11-27

--- Log opened Sun Nov 27 00:00:01 2016
shornesmaller spam send to gdb patch list now01:20
olofkshorne: Is it really a byte access? Isn't it an unaligned word access (again, I should probably learn C some day :))15:24
olofkand good job with the patches15:24
kc5tjaolofk: Question for you, if I may.15:24
kc5tjaolofk: If I have a processor design, and I develop some support modules intended to go with it, should I place those modules in the same repo, or should they go in separate repos?15:25
kc5tjaFor example, I developed what I believe is a good Wishbone bridge to my CPU's native bus, and right now it's just kind of "floating about" in the example documentation in the datasheet/docs.  But, I think it could be of use in general too.15:27
olofkkc5tja: If they're all dealing with your CPU/bus and are quite small, I think you could put them in a single repo17:04
olofkFor the wishbone stuff, I decided to put the arbiters, data resizers and CDC component in the same repo as they're all dealing with interconnects17:06
olofkThe BFM however, is in a separate repo17:06
olofkBut as long as no one else is using the code, I'd say it's more or less down to personal taste17:08
kc5tjaOK, I'll re-arrange the repo to include the different components in different directories.17:12
shorneolofk: you are right, its different because its word access.  FYI, with newlib users can setup their own exception handlers in the "userspace" program. I guess we can suggest this for this case.20:25
--- Log closed Mon Nov 28 00:00:03 2016

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