| --- Log opened Wed Nov 09 00:00:34 2016 | ||
| -!- ChanServ changed the topic of #openrisc to: Official OpenRISC Project channel | http://openrisc.io | http://orconf.org | mailing list: https://lists.librecores.org/listinfo/openrisc | git: https://github.com/openrisc | IRC logs: http://juliusbaxter.net/openrisc-irc/ | FOSSi: http://fossi-foundation.org/ | LibreCores: https://www.librecores.org/ | 00:04 | |
| @juliusb | hi all, I've updated the IRC logs to omit joins/quits as it's very noisy. I hope you don't mind | 01:18 |
|---|---|---|
| kc5tja | +1 | 01:31 |
| @olofk | Finde: We've been using verilator a lot in the OpenRISC project. You can check out some example testbenches in the FuseSoC core library (orpsoc-cores) | 02:10 |
| @olofk | Regarding VPI, I took a look at that a while ago, and I think verilator only supports calling vpi from the c++ testbench... which is quite awkward | 02:11 |
| @olofk | Hey, I'm op now :) | 02:11 |
| @olofk | thanks juliusb :) | 02:11 |
| Finde | thanks olofk I'll probably have a look once things calm down a bit | 09:36 |
| --- Log closed Thu Nov 10 00:00:36 2016 | ||
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