IRC logs for #openrisc Tuesday, 2016-11-01

--- Log opened Tue Nov 01 00:00:22 2016
promachhow do I use to compile mor1kx and DMA together ?04:55
SMDwrkpromach: what have you already tried?05:09
SMDwrkvidya: hi, do you have any success with verilated run?05:09
promachSMDwrk: actually now, I am using Zedboard, having much problem with AXI DMA module.05:51
promachI am considering the possibility of using mor1kx and DMA05:52
promachneed to go now05:52
vidyaSMDwrk: I'm still stuck at that error06:43
SMDwrkvidya: how do you compile your binary?06:43
SMDwrkI'm still working on getting data from uart06:43
vidyaSMDwrk: I tried simulating with icarus also but no luck some other error pops up06:44
SMDwrkwhat kind of error?06:44
vidya or1k-linux-musl-gcc hello.c -o hello.elf06:44
vidyaI use this command for compiling06:45
SMDwrkTry or1k-elf toolchain06:45
vidyaWhen using this :fusesoc sim --sim=icarus wb_sdram_ctr , the toolchain works, but when fusesoc sim --sim=icarus mor1kx-generic --vcd --elf-load=/home/vidya/or1k/csaw_esc_2016/tools/c_codes/hello.elf06:46
vidyaI get this error::0: assert: failed assertion 0 Aborted (core dumped) ERROR: Failed to build simulation model ERROR: Failed to compile Icarus Simulation model06:47
vidyaI will try using or1k-elf06:47
SMDwrkDo you have any logs for that assert?06:47
vidyaSorry I mean simulation works06:48
vidyaMaking jtag_vpi-r2.vpi from  jtag_vpi.o... Array too big [4294967295:0]:0: assert: failed assertion 0, Before this it just compiles elf , jtag06:49
vidyaSMDwrk: Verilator worked with or1k-elf-gcc, Thanks a lot.  But why is it so? which one is the latest?06:59
olofk_vidya: The or1k-elf and or1k-linux-musl toolchains have different purposes07:02
olofk_You often need both07:02
vidyaIs it so that or1k-elf is used to compile for simulation and or1k-linux- is used for running the code on linux?07:04
ZipCPU|LaptopSMDwrk: Have you made any more progress on that UART?07:05
ZipCPU|LaptopCan you see the UART output line toggling (yet)?07:05
ZipCPU|LaptopIf you can get it at least that far, I can get you the rest of the way.07:05
SMDwrkZipCPU|Laptop: sure, i see tx pad differs through time and it looks like some uart signals, but I didn't have time to make your uartsim to capture that correctly, that's why I still don't have any output to the stdout07:06
ZipCPU|LaptopTwo next steps: 1) Make sure you are using the uartsim.cpp from the wbuart32 repository.  There was a bug that was fixed after sending the UART your way.07:08
ZipCPU|Laptop2) Transmit an "A" or some other similar signal with transitions one bit period apart.  Count the clocks between transitions, and make sure the baud rate is set up properly.07:08
ZipCPU|LaptopThere's a "setup" line when calling the UART, where you need to give it the number of clocks between transitions.07:09
ZipCPU|LaptopRemember, these are clock ticks.  There is one clock tick for every time the clock has a high value and a low value, even though the simulation goes through the loop two times.07:09
ZipCPU|LaptopThe reason for the updated uartsim is that my internal state machine counting was off by one tick.07:10
ZipCPU|LaptopSimulation found that bug, and so it's been fixed.  Without updating, you should be able to run at a large number of ticks per baud interval.07:10
ZipCPU|LaptopOh ... one other thing to keep in mind, just a sad fact of life today: The uartsim baud rate is not changed when you adjust the baud rate within your code.07:11
ZipCPU|LaptopThe baud rate you set in your code must match that of the uartsim, or ... you'll have some of the standard baud mismatch problems.07:12
SMDwrkI hope to try this today07:15
-!- Thomas_ is now known as Guest8387510:29
N0xsysHi there!12:56
N0xsysI have a little question about OpenOCD12:56
N0xsysIn the OpenOCD terminal, you can use the 'reg' command to print the list of the registers and their values12:57
N0xsysBut how can I say in my Verilog code that one particular register should be visible by the OpenOCD reg command ?12:59
wallentostekern: I am updating the lk port, okay? Some important changes in the code base that stop or1k from building13:02
RelaxAtionhello all15:17
RelaxAtionI am havong some difficulties on implementing interruptions on an OpenRisc core and i hope to find some help in here15:21
RelaxAtioni already put UPR[PICP] at 1 to enable programmable interruption then i put the PICMR register at 0x00000000 because i don't want unmasked interruptions15:25
RelaxAtionthen i put my PICSR register at 0x00000003 because i want 3 programmable interruptions ut now i don't know what to write on my verilog file to work with the interruptions15:27
RelaxAtioni don't know if i am clear enough sorry15:27
ZipCPUWell, here's the best help I can offer: Don't leave the forum.15:27
ZipCPUMany of those who understand the OR1K architecture the best respond within 24-hours.15:28
ZipCPUIf you must leave the forum, then check the logs at
RelaxAtionah ah ok i'll let my IRC client open all night then !15:28
ZipCPUExactly!  (Especially since I don't know the answer to your question ...:)15:28
RelaxAtionin fact my question is more a verilog issue than an openrisc issue i think15:29
olofk_RelaxAtion: What are you using on the software side? or1k-elf (aka the newlib toolchain)? Or do you run for example Linux?15:33
olofk_And what will you use to trigger the interrupt? An external signal from a peripheral controller, or something else?15:34
RelaxAtioni run for an example linux and the interrupt should be triggered by an signal emit when a condition is reached15:35
olofk_If you run Linux it will likely be a lot more complicated15:36
olofk_Not sure how interrupts work at all in Linux to be honest15:37
olofk_You would probably need to write a kernel driver15:37
olofk_Unless you're talking about software interrupts, but I'm not sure how that work either15:39
olofk_I should probably have learned this by now after spending five years of my life on this stupid CPU :)15:39
ZipCPU\o/ !15:43
olofk_mafm: I heard you talked to the Software Freedom Conservancy at debconf :)15:49
RelaxAtionok i discussed with my colleagues and apparently we are working with or1k-elf :)15:50
olofk_RelaxAtion: ok. That will make it simpler15:51
olofk_But what is the source of the interrupt? You say when a condition is reached. Do you mean in some verilog code outside of the CPU, or a condition in some software running on the CPU?15:52
RelaxAtionmisspress soryr15:57
RelaxAtionso we have an altera card, with a cyclone 4 on it15:57
RelaxAtionand there is some verilog code running on it15:58
olofk_So far so good :)16:00
olofk_I got to run for a while now, but please explain a bit more and I'll try to help when I get the time16:01
olofk_Also look at this. It might be what you need
RelaxAtioni am preparing my words, see you :)16:01
olofk_Perfect! :)16:01
RelaxAtionso, we detect a jal, we read the adress in the R9 register, we put it on a pile, then when we detect a jr we check the last adress stocked in the pile and the current adress in R9, if their is a difference the interrupt is trigger17:06
ZipCPURelaxAtion: Are you doing this in simulation, or in hardware?17:21
ZipCPUAnd ... what do you mean by "put it on a pile"?17:21
RelaxAtionit is made for hardware17:22
RelaxAtionand we create a pile where we stock the adress that's why i said put it on a pile :)17:22
olofk_RelaxAtion: Ah cool. So you have a hardware stack that runs in parallel to the regular stack, and you detect mismatches.17:25
olofk_How big is your pile?17:26
olofk_I've seen small CPU that only have a hw stack, like 8 entries, never using both sw and hw17:27
RelaxAtionyes that is the point, we have to develop a defense for FPGA :) our pile isn't that big, less than 30 slots i think, i don't rememeber sorry :/17:28
olofk_ok, cool. So then I guess your hw stack (or pile) will generate the interrupt, right?17:28
RelaxAtionwhen the mismatch is detect the interrupt is supposed to be generate but we are struggling on how to create this part17:30
olofk_Have you seen in simulations that the interrupt signal is being sent? Is it connected to one of the bits in the irq port on the CPU?17:31
olofk_Which CPU by the way? or1200 or mor1kx.17:32
olofk_I hope mor1kx, because we really want people to move away from or1200 :)17:32
RelaxAtionwe work on mor1kx don't worry ;)17:33
RelaxAtionwe are in cappucino on it17:33
olofk_And FuseSoC to build the system?17:33
RelaxAtionoh yes fusesoc17:33
olofk_You got top grades, then! :)17:34
RelaxAtionnon because the interrupt signal isn't created yet, that's where i am struggling17:34
RelaxAtionah ah nice then :)17:34
olofk_ok, so you don't have an interrupt signal yet? Did I understand that correctly? Or do you have one, but can't make the CPU see it?17:35
olofk_I'm talking about a interrupt wire to the CPU here17:36
RelaxAtionwe don't have an interrupt signal yet17:37
RelaxAtionit is still only a dream ahah17:37
olofk_I would recommend starting with that actually. It will make it much easier to see that the software works17:39
olofk_But say that you have a interrupt wire connected to bit 14 in the irq_i vector of mor1kx17:40
olofk_You would then add an interrupt handler with or1k_interrupt_handler_add to register the function to be run when the interrupt triggers17:41
olofk_You would then run or1k_interrupt_enable to enable interrupts in general17:41
olofk_And or1k_interrupt_enable to enable your specific irq line17:42
olofk_oh, the first one should be or1k_interrupts_enable, not or1k_interrupt_enable17:42
olofk_Is this for csaw esc btw?17:46
RelaxAtionthank you ! i'll try to implement this tommorrow morning ! yes you guessed right :)17:47
olofk_Good luck. It looks like a cool challenge17:48
RelaxAtionit is a really nice experience, but it is really tough, we have to discover and implement a defense in a whole new system in 2 months :)17:50
RelaxAtionwhen you add your classes and others projects you don't have a life anymore ahah !17:51
olofk_Haha. I was just thinking it would be nice to go back to school for a while to have some time to do other projects :)17:52
-!- olofk_ is now known as olofk17:52
RelaxAtionwell it's my last year but i can still exchange plaes with you ;)17:55
RelaxAtionanyway thanks for your help, i'll come agin when this work ! :) good night all18:03
olofkWelcome back18:09
mafm1olofk: where did you hear that?  I didn't even attend last Debconf18:38
olofkmafm1: Hmm... who could that have been then? I talked to a guy at the GSoC mentor summit about our gcc situation and he said he talked to someone at debconf about the same issue a few weeks ago18:51
olofkI asked if it was you, and he said yes. He must have mixed up the names then, but still, I wonder who it was then18:51
mafm1olofk: gsoc mentor for Debian, or other projects?18:57
mafm1maybe I did in last Debconf, a year ago :)19:01
olofkmafm1: No, his name was Bradley Kuhn (I think) and he was from the Software Freedom Conservancy19:06
olofkTime to sleep. Good night19:07
mafm1olofk: ah, right, maybe it was another person, because I think that I never spoke to him... although I would have liked to19:07
mafm1olofk: nite :)19:07
--- Log closed Wed Nov 02 00:00:24 2016

Generated by 2.15.2 by Marius Gedminas - find it at!