| --- Log opened Sat Oct 29 00:00:18 2016 | ||
| SMDhome | olofk_: Hi, I'm struggling with getting uart to print something using verilatpr and ZipCPU help. Could you tell where can I look at how is everything gets connected together? | 09:21 |
|---|---|---|
| SMDhome | I see some data on wb bus for uart, but there is no wb_cyc signal for it and I think this might be a problem in my case | 09:21 |
| ZipCPU | SMDhome: I'm always pleased to hear any time my CPU can help you debug OpenRISC. ;P | 09:56 |
| vidya | Hello all, I have added a new verilog module in the mor1k core and I would like to check the behavior of the changed system by simulating using verilator. | 10:30 |
| vidya | It seems that fusesoc uses sources from the github page and doesnt reflect the local changes. Can anyone help me regarding how to reflect the change i have incorpoarated in simulation? | 10:31 |
| ZipCPU | Yes. Once it downloads the changes from github, it doesn't download them again until explicitly told to do so. | 10:32 |
| ZipCPU | Feel free to edit those local pages to the extent that you need to. | 10:32 |
| vidya | Ok | 10:42 |
| SMDhome | olofk_: nevermind, I've found the problem | 11:08 |
| --- Log closed Sun Oct 30 00:00:19 2016 | ||
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