IRC logs for #openrisc Sunday, 2016-10-16

--- Log opened Sun Oct 16 00:00:59 2016
kc5tjaI doubt it.00:41
kc5tjaWIP datasheet for KCP53000 CPU -- .  Let me know what you think!01:02
promachI am now figuring out how to synthesise openrisc mor1kx with yosys03:06
promachanyone have links for this ?03:06
SMDhomepromach: could that help?06:52
promachSMDhome: not really07:00
promachunless I missed some link within it ?07:00
promachI even saw
SMDhomekc5tja: .svg file is not shown inside text but available directly. Ialso thing it would be nice if you add some bus names to it. Everything else looks nice.07:01
promachbut no exact tutorials on how to do it07:01
SMDhomeI guess there are no exact tutorials on that. Do you want to build mor1kx using yosis and then upload it to lattice fpga or smth else?07:02
SMDhomepromach: Then I'd suggest to try that part of my link:07:05
SMDhomeyosys -p "synth_ice40 -blif rot.blif" rot.v07:05
SMDhomearachne-pnr -d 1k -p rot.pcf rot.blif -o rot.asc07:05
SMDhomeicepack rot.asc rot.bin07:05
SMDhomeiceprog rot.bin07:05
SMDhomesynthesize - pnr - pack - flash07:05
promachpart of your link ?07:05
SMDhomeThere is caption "How do I use the Fully Open Source iCE40 Flow?"07:06
promachI see07:07
promachthis targets a single standalone verilog file07:07
SMDhomeOk, then we need to ask olofk how to get compilation line for mor1kx for icarus sim from fusesoc07:08
SMDhomepromach: do you have fusesoc?07:10
promachthat was installed on my old laptop07:10
promachI need to get it here on my new platform07:10
promachby the way, I am new to openRISCC07:11
SMDhomeI suggest you to get it or at least take a look at git repo: ie there is smth like systems/de1/rtl/verilog/orpsoc_top.v which I guess is wrap(top file) for SoC for de107:12
promachgive me 10 minutes07:12
SMDhomeAnd I think you should use yosis like: firstly configure mor1kx core(choose pipeline and features you want) and then yosis orpsoc_top.v -I<list all directories than contain files>07:14
SMDhomepromach: >by the way, I am new to openRISCC07:14
SMDhomeMe neither :)07:14
promachwow, you are to humble07:15
promachI am not using DE107:16
promachI do not have DE107:16
SMDhomethat is only example07:17
SMDhomepromach: check here
promachhow do I get the latest code for mor1kx with fusesoc ?07:19
promachlet say I simulate and synthesise without any thought of any specific FPGA architecture07:20
promachhow would I do it ?07:20
SMDhomepromach: let's clarify, there is mor1kx core and there is SoC that uses mor1kx core and has interfaces to memory, jtag, etc07:22
SMDhome<That's the time olofk_ should trigger after naming fusesoc so many times :)>07:22
SMDhomeYou download and install fusesoc, then for simple simulation you could just run: fusesoc sim --sim=verilator/icarus mor1kx-generic --elf-load=bla.bin07:22
SMDhomemor1kx-generic serves only for simulation purposes07:23
promachSoC that uses mor1kx core ?07:24
SMDhomeAre you familiar with SoC term or should I explain?07:24
promachSystem on chip07:24
promachyou are saying that I need SoC besides the core ?07:25
promachI am really confused now07:25
SMDhomeYep, SoC could contain cpu core, mem controller, some periph connected to a bus, while mor1kx - is just a cpu core07:25
SMDhomeSo fusesoc makes SoC for you07:25
promachfusing all peripherals together with mor1kx ?07:26
promachlet me try simulation07:26
SMDhomepromach: do you have myStorm board or icoBoard?07:27
promachnot yet now07:28
promachI have Parallella Desktop or some other Altera board07:28
promachI have error07:28
SMDhomeDo you really have a binary at /home/phung/bla.bin?07:29
SMDhomeAnd is it really elf for openrisc?07:30
promachI just ran07:32
promachfusesoc sim --sim=icarus mor1kx-generic --elf-load=bla.bin07:32
promachand did nothing else07:32
SMDhome--elf-load=bla.bin - you pass binary file to be executed on your simulation07:34
SMDhomeDo you have a toolchain for openrisc?07:34
promachI also need to get this as well07:36
SMDhomeSure. I could get you a binary that prints from 1 to 100 so you could test fusesoc07:37
olofk_I heard you calling!07:40
olofk_But actually, I just logged in to temporarily shut down this computer for a little while. Sorry about that. I'll be back in a while to show the insurmountable powers of FuseSoC07:42
SMDhomeolofk_: since wallento is afk, do you know anything about optimsoc and how to use it for running multi-core setup for mor1kx?07:42
olofk_I did try to build a basic OpenRISC-based SoC with icestorm a while ago too. Never completed it07:42
SMDhomeor should I stick with
olofk_SMDhome: I don't know much about the internal details, but it seems like they have put some effort into documentation and build/simulation scripts07:43
olofk_Sorry. gtg07:43
promachSMDhome: can I use ?07:50
SMDhomepromach: I have never tested that, I'm using newlib toolchain for baremetal :(07:53
ZipCPUpromach: olofk will come back.  He's a wonderful OpenRISC resource here, one of the few who tends to answer channel comments.08:11
ZipCPUWhat you may be missing is the flow: Yes, FuseSoC is used to aggregate various components together into a composite whole.08:11
ZipCPUFuseSoC aggregates existing known components, such as SMDhome explained: CPU, memory controller, UART, etc.08:12
ZipCPUFuseSoC, though, needs a system component to do so.08:13
ZipCPUThe system component tells FuseSoC what components to get, how to aggregate them, etc.08:13
ZipCPUIt's sort of the "toplevel" of a design.08:13
olofkHappy to be back. Thought for a while that my trusty rPi had given up for good08:47
-!- knz_ is now known as knz10:36
kc5tjaSMDhome: That is a rendering bug on the part of the web browser.  I have no control over that, I'm afraid.  :(13:06
kc5tja(the lack of bus names and register names in the block diagram; if anyone has ANY idea how to fix this, please PLEASE let me know.)13:06
kc5tjaFor those wondering, you can synthesize a design with multiple Verilog components by simply listing all the components on the command-line.  Throwing them all in a directory D and doing something like "yosys -p '...' D/*.v" is sufficient.13:08
ZipCPUkc5tja: I may not know the answer to your requested problem, but ... can you at least describe the problem?13:38
ZipCPUI'm looking for the reference of the block diagram with neither bus names nor register names in it.13:38
ZipCPUCan you tell me where I should look?  What format the diagram is in?  etc?13:38
kc5tjaZipCPU: The diagram is here:
kc5tjaZipCPU: But if you open the file in Inkscape, you'll notice that everything is labelled correctly.17:20
ZipCPUkc5tja: Try this: "inkscape -D -z --file=block-diagram.svg --export-eps=block-diagram.eps"20:46
ZipCPUThat should maintain the quality of the svg image, while turning into a ... more usable format.  ;)20:46
kc5tjaI cannot view EPS on the web.20:47
kc5tjaNot as an inline image.20:47
ZipCPUkc5tja: Yes, but you can use ghostscript to convert eps to png16m, which you _can_ then view on the web.21:35
ZipCPUDon't forget to make certain you have some number of text alpha bits set.21:37
ZipCPUkc5tja: Okay, so I tried it out, although I used Image-Magick instead of ghostscript.  Here's the result:
ZipCPUCommands used: inkscape -D -z --file=block-diagram.svg --export-eps=block-diagram.eps21:51
ZipCPUFollowed by: convert block-diagram.eps -flatten block-diagram.png21:52
ZipCPUI'm sure you could do more with ghostscript--perhaps even to get the text to look better, but this was easy and simple.21:52
kc5tjaI really wish Firefox and Inkscape would just bloody cooperate.  I wouldn't have to go through these crazy-as-fsck gyrations just to get something that can display and print equally well.  >:/22:04
ZipCPU|Laptopkc5tja: I use this wonderful program called 'make' ... it makes the gyrations less painful.22:10
kc5tjaNo, it just automates the process.  The pain remains.22:17
kc5tjaI have to now maintain two sources of documentation, one for PDF, and one for the web, if I want to get good quality output.  And that's just stupid in my estimation.22:17
--- Log closed Mon Oct 17 00:00:00 2016

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