IRC logs for #openrisc Friday, 2016-09-23

--- Log opened Fri Sep 23 00:00:24 2016
olofkkc5tja, ZipCPU : I am using the same definition as kc5tja for pipelining02:14
olofki.e. pipeline != burst02:14
olofkBoth pipelining and bursts can help mitigate high latency02:14
olofkAnd both MicroBlaze and mor1kx uses bursts to fill the caceh, but not pipelining02:15
olofkAlso, bursts are more friendly to memory controllers, since it can predict the address of the next access, which helps if it wants to send a burst request to the memory02:20
olofkIt's also easier to change bus width of a burst02:20
olofkFor pipeline accesses, you have no knowledge of the next transaction02:21
wallentopipelining is a natural feature of AXI02:32
wallentobecause of the channels02:32
olofkwallento: True02:34
olofkBut that doesn't mean that the master will use pipelining02:35
olofkWith uBlaze as the example, it will only have one transaction (single or burst) in flight at the same time on a bus02:35
wallentoyeah, thats correct03:06
wallentomost AXI interconnects are actually shared medium stuff03:06
wallentobut at least interleave transactions on the slave side03:07
wallentobut where it is generally superior to classical busses is hierachies03:07
shornewallento: did you see my message about building musl + or1k gcc-5.3.0?  I did the update for or1k-gcc-5.4.005:41
ZipCPU|Laptopshorne: Do you know of any other locations on the net, besides OpenCores, where the Wishbone B4 spec is posted?06:20
olofkZipCPU|Laptop: Doh... not sure actually. Didn't think of that06:31
shorneI was looking at the (while looking at the stuff from opencore, wishbone spec is one)06:34
shorneI think I found it...06:34
shornecached06:35 is down now, we can try that later06:37
ZipCPU|LaptopNo .... that doesn't work, as it that copy strips out all the images.06:37
ZipCPU|LaptopI mean ... the spec itself isn't the problem.  I have a copy of it, and I'm sure many others do as well.06:39
ZipCPU|LaptopIt's just that ...  there needs to be a public place on the web where it is posted.06:39
stekernpersonally, I'm just happy if the B4 spec vanishes06:40
ZipCPU|LaptopI'm looking forward to a nice, simplifying rewrite.  Sounds like you have another opinion, stekern?06:47
ZipCPU|Laptop(BTW -- I'll make my rewrite comments/proposal at ORCONF ...)06:48
stekernno, I think an update B3 that would make things clearer would be great. Adding new features would also be great, it should just not have been done as it was done in B406:56
stekern(and I'm not speaking about technical objections)06:56
shorneah, something wrong with my connection06:58
ZipCPU|Laptopstekern: The only problem there is that the only mode I use is the pipeline mode in B4.06:59
ZipCPU|LaptopUsing that mode, I can transfer up to one transaction per clock.07:00
stekernyeah, as I said, I don't really have any technical objetions against the pipeline mode that was added in B407:00
ZipCPU|LaptopB3 limits the bus speed to one transaction every three.07:00
stekernI know (except for bursts) or in async mode07:01
olofkThere have been some background work on finding a new home for Wishbone since earlier this summer. More details are orconf :)07:04
shorneolofk: cool looking forward to it07:10
ZipCPU|LaptopI know there are "issues" relating to B4, but don't know what they are.  Are they discussed online anywhere?07:18
stekernthere's this irc channel on freenode called #openrisc, I think they have been discussed there several times ;)07:32
olofkZipCPU|Laptop: I think I have explained that already07:33
olofkShort story; The changes were done by someone who was not really driving the development of the spec, and they added a lot of restrictions on how the spec can be used and shared07:36
olofkAs an attempt to make them controlling the standard07:36
olofkThe steward of the spec has asked for the revision to be amended, but he is also happy to make updates to the spec. As long as they keep the spec in the public domain07:37
wallentoshorne: yes, I saw, thanks. Should we move GCC forward then?07:39
shornewallento: I think so, I think we can just push the releases to branches and create releases07:48
shorneand bump musl-cross version07:48
shornewant me to push? I dont think I have rights on or1k-gcc07:49
shorneI just did a full build, musl, busybox, strace07:50
shornewith latest gcc 5.4007:50
shorneand packed in linux07:50
shornelets see if I can reproduce this old bug from poke53281 with strace07:50
wallentoI will give you the admin rights07:53
wallentoI am in Italy already and have limited connectivity07:53
shorneah, alright, how is it there?07:57
wallentoexcellent, four weeks holidays in Tuscany, what can be better :)08:21
olofkwallento: orconf? :)08:25
shorneTuscany is a nice place, been there 2 times08:29
shornenot for 4 weeks though08:29
ZipCPU|LaptopFascinating: "GNU is not in the public domain."  (wikipedia/Copyleft), Public domain is ... "the realm embracing property rights that belong to the community at large, are unprotected by copyright or patent, and are subject to appropriation by anyone", B4: "Notice is hereby given that this document is not copyrighted, and has been placed into the public domain"08:37
ZipCPU|LaptopB4 p3, on B4 p2: "This ebook is Copyright 2010 OpenCores."08:38
ZipCPU|LaptopLegally, this would be a contradiction.08:38
olofkZipCPU|Laptop: Compare the usage restrictions between the b3 and b4 spec and you'll see08:41
ZipCPU|LaptopSuch usage restrictions are in conflict with the "public domain" statement.08:41
ZipCPU|LaptopIf the document truly is in the "public domain", no rights remain whereby to enforce usage restrictions.08:42
olofkZipCPU|Laptop: Legally, the changes that ORSoC did to b4 probably aren't valid08:43
olofkIANAL :)08:43
shornewell, my build of strace is not working, not sure if its the bug or the strace build08:48
wallentoolofk: vivado for fusesoc got some rework13:29
wallentobut ready to merge13:29
wallento*some small things around VHDL missing13:29
kc5tjaThe document is explicitly licensed as public domain (per the document itself), so if ORSoC attempts to regain control over B4, they'll flatly lose their case in court.13:32
kc5tjaAs soon as ORSoC printed that license grant on the document, they've given up all rights to the contents of the document.  So, have at it!  I've often wondered if a Wishbone 2.0 were in the works.13:34
kc5tjaThe only part I'm not sure of on a legal basis is whether or not a derived work can continue to use the Wishbone name.13:34
ZipCPU|Laptopkc5tja: But ... who owned the name during the B3 publication?  Surely they retain ownership to this day, no?13:53
ZipCPU|LaptopHmm ... Looks like and Silicore declare ownership in it.13:54
ZipCPU|LaptopSo ... were a new specification to be developed, what would be the appropriate license?  Creative Commons?13:55
ZipCPU|LaptopCC:BY-SA?  Specifically, the Creative Commons license whereby copying requires attribution (BY), and "licensees may distribute derivative works only under a license identical ("not more restrictive") to the license that governs the original work (SA).  Would that be a valid/better/more appropriate license?14:09
kc5tjaSilicore, I think.  But they're out of business.14:26
kc5tjaZipCPU|Laptop: I think CC:BY-SA is a step in the right direction.14:27
kc5tjaI think we'd need more detailed license study to conclude if it's the ideal license for OpenCores' needs though.14:27
kc5tjaBut, definitely better than nothing.  :)14:27
kc5tjaHonestly, though, I often wonder if the specification would be better kept in a Github repo along with some Verilog reference modules to serve as an illustration and compliance test.14:29
kc5tjaThat is, just lay the Wishbone spec project out like any other opencores project, with rtl/verilog holding the reference implementation for the spec, and doc/ holding the spec and/or datasheet itself, etc.14:30
ZipCPU|LaptopIIRC, there were at one time verilog reference modules with WB for that purpose.14:45
kc5tjaI find the project listing pretty ephemeral.  I've seen a ton of projects disappear.  That's why my Kestrel cores follow the OpenCores directory layout (more or less), but I've not submitted them to that site.15:53
olofkkc5tja, ZipCPU|Laptop : I've been working on Wishbone BFMs, IP-XACT bus descriptions and other infrastructure around Wishbone for quite a while. The intention is to put this up on LibreCores some kind of Wishbone reference package17:18
olofkwallento: Saw the PR. Will look at it more closely in the coming days. Also a bit amazed that this was the 120th PR for FuseSoC :)17:21
olofkdoh. Need to fix the appveyor CI stuff too :/17:22
olofkwallento: Thanks for the PR. Almost there. Left some comments for you. Ping me if you have questions. I can amend it locally if you like also17:51
olofkGood night17:51
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cw200100Hello! I have a question about setting a gdbserver within linux running or1k-sim. I am currently using the or1k-linux-musl toolchain and so far I was unable to compile the sources from, as it does not support openrisc as a host. The old svn sources from seem incompatible wi18:26
cw200100Can anyone provide any pointers as to how I can setup gdbserver and have it within or1k linux? Is there any other repo I should use to compile it? Thanks!18:26
ZipCPU|Laptopcw200100: Welcome to the forum.  While I can't answer your question, I can share with you the one big mistake other questioners have made, and encourage you not to make it: Don't leave the forum.19:14
ZipCPU|LaptopUsually questions get answered within 24 hrs or so, but if you leave the forum, you won't get your answer.19:14
cw200100Hello ZipCPU, thank you for the feedback! I appreciate it19:16
ZipCPU|LaptopYou might find that shorne is the person to ask, since he's getting ready to discuss gdb and or1k at the next ORCONF.19:17
cw200100I see, it's good to hear that the next ORCONF will cover gdb as well. I have been looking for quite some time to figure out how to debug a linux process running on or1k-sim+vmlinux, and the only way (known to me) is to use a gdbserver. Unfortunately, the sources I found seem outdated/incompatible.19:33
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ZipCPU|Laptopshorne_ would you recommend gdbserver as a means of debugging?22:15
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--- Log closed Sat Sep 24 00:00:26 2016

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