IRC logs for #openrisc Friday, 2016-09-09

--- Log opened Fri Sep 09 00:00:03 2016
olofkAny other way to sleep for an amount of time with a bare-metal or1k program?05:20
olofkaha. Maybe I should try the timer functions in libgloss05:31
olofkwallento: You know these things, right? How do I use the timer to implement a simple usleep?05:34
wallentoI will tell you if you update http://openrisc.io/newlib/tutorial.html afterwards ;)05:35
olofkI found this! :) http://openrisc.io/newlib/docs/html/group__or1k__timer.html05:35
wallentoshit, you already found it05:37
wallento:-D05:37
wallentoI think you wanna use the timer handler stuff05:37
wallentothe default handler just increases ticks05:37
wallentoso either you wait for the ticks to increment or set your handler05:38
olofkWaiting seems easier. It's just a single thread05:38
olofkSo, init, enable and then read get_ticks until I'm happy with the value there?05:39
olofkThe good thing is that I can just do a quick test program and run it in icarus to check05:40
olofkWith more or less the same RTL as in HW05:40
olofk(except for mem controller. I replaced that with a simulated Avalon memory instead)05:40
wallentoyes, that should work05:43
olofkWorks fine05:55
olofkor maybe not06:10
olofk...or maybe06:12
olofkAha. Looks like I set the timer frequency too high, so it never got time to do anything before the next interrupt06:16
stekerndoesn't it read the ticks directly from the timer?06:17
olofkI haven't really figured out all about the timer yet06:19
olofkwallento: What on earth is this good for? while (ticks == or1k_timer_get_ticks()) { }06:20
olofkIt looks like this will only exit when ticks == 006:22
stekernit will exit when ticks != or1k_timer_get_ticks()06:23
olofkoh, right06:23
olofkI suck a tC06:24
olofkat C06:24
olofkand writing06:24
stekernstop sucking tC06:24
olofk:)06:24
stekern;)06:24
olofkLooks like or1k_timer_get_ticks only return 006:25
olofkMaybe I should run it on the board instead06:26
olofkI can see that the ttcr register is moving in the waveform, but still nothing from get_ticks06:36
stekernI repeat, does the get_ticks read the ticks directly from the timer (+ the accumulated periods)?06:39
stekernI seem to remember that there was something odd with get_ticks like that, but I might well remember wrong06:40
stekernright, "ticks" is number of accumulated periods06:57
stekernmaybe that's fine for you? but I recall that I needed finer granularity than that for something sometime07:19
wallentoI think you can set the granularity too07:28
wallentohttp://openrisc.io/newlib/docs/html/group__or1k__timer.html#gaf760867d2f9d04f0c101c4c4975b061607:29
wallentovoid or1k_timer_set_period (uint32_t  hz) 07:29
stekernyes, but then you increase the interrupt frequency07:29
stekernand I wanted to run without the timer exception enabled07:29
stekernafair07:29
wallentoah, Isee07:31
olofkI still don't get it07:46
olofkI love the heartbeat parameter that I added to vlog_tb_utils07:53
olofkusesoc sim zem4310 --elf-load=timer.elf --timeout=30000000 --heartbeat=100000007:53
olofkf07:54
olofkTells me I have time to get a coffee before the sim is finished :)07:54
wallentothe timer generates interrupts and the default handler increments the ticks08:12
wallentoyou can set your own handler and change the frequency of interrupts08:13
wallentoor turn it to one shot etc.08:13
olofkhttp://22d649fe06df7da7.paste.se/08:13
olofkI run this for 30us08:14
olofkIf I got this right, I should get a interrupt every 20us08:14
olofkAlso, if I raise the frequency to 100000 it stops working08:15
olofkI just looked quickly at the VCD, but I think it doesn't have time to finish the interrupt before a new one comes in08:15
olofkThe CPU runs at 50MHz08:15
wallentothats 1000 cycles08:23
wallentoif that is the issue you probably have to build something yourself with a one-shot timer then08:24
wallentoah, wait08:24
wallentoor set your own handler and count up to a your value in the handler08:24
wallentowhen you reach it, disable the timer08:24
wallentobut it will not be precise then08:25
wallentobecause you are reaching the limits08:25
wallentoif it needs to be more precise you should probably use it as stekern described08:25
olofkIt doesn't have to be very precise. Just want to sleep for a while, say 500 us08:29
olofkBut I still don't get what's wrong08:29
olofkWith or1k_timer_init(50000), the tick should increse every 20us, right?08:30
olofkThe high frequency I'm using now is just so I don't have to simulate forever08:31
olofkOr did you mean that 50000 is also too high?08:31
_franck___I don't know how the timer works in openrisc but in general if I have to do that on a microcontroller, I set timer count frequency to 1┬Ás, preset its value to 20 and while(!timer_expired_flag);08:41
_franck___you don't need interrupt overhead08:41
olofkTrue08:44
olofkSo we should probably add a function to get the ttmr value too08:47
olofkAnd for now I'll read it out directly from the reg08:48
olofkttcr I mean08:49
olofkMuch better!08:52
olofkticks = or1k_mfspr(OR1K_SPR_TICK_TTCR_ADDR);08:52
olofkHmmm.. but why does it stop at 1955 ?08:53
olofkMaybe I should read up on the timer in the spec08:57
wallentoI second that ;)08:59
olofkok, almost09:03
olofkahh.. enabling the timer without an interrupt handler is of course bad09:13
olofkBut I don't need interrupts09:13
olofkAhhh!!! How to I make the damn timer start?09:25
shorneor1k_timer_restore(timerstate);09:26
shornenow sure what you are doing though09:26
shornehttps://github.com/openrisc/tutorials/blob/master/sw/timer/timer.c09:26
olofkRight now I'm just trying to figure out how this thing works09:27
_franck___olofk: http://git.pengutronix.de/?p=barebox.git;a=blob;f=arch/openrisc/lib/clock.c;h=a171214a5379f7719ae26698689b359128432fb3;hb=HEAD#l2509:28
olofkI don't want any interrupts. I just want to set the timer to 0 and start counting09:28
_franck___I might remember I needed mtspr(SPR_TTMR, SPR_TTMR_CR | 0xFFFFFF); or it didn't start to count09:28
olofkBoth are set to 0 in my test code09:30
olofkBoth ttmr and ttcr09:30
olofkAnd then I set the mode to 0x3, which should be free-running clock09:30
shorneyou want to se TTMR_M to start incrementing ?09:32
olofkYes. I'm setting it to mode 0x3 now09:33
shornewhen TTMR_M TTCR keept counting forever09:33
olofkor1k_mtspr(OR1K_SPR_TICK_TTMR_ADDR, 0xc0000000);09:33
olofkAnd before that I set both TTMR and TTCR to 009:34
shorneso you can just read TTCR every few cycles09:34
shornebut TTCR is not incrementing?09:35
olofkexactly09:35
shornewhat about UPR_TTP?09:35
olofk?09:35
shornetimer exists?09:35
shorneUPR[TTP] specifies whether09:35
shorneor not the tick timer facility is present09:35
shorne(from spec) just a sanity check09:35
olofkI have gotten it to work, but not with my code09:35
shorneI see09:35
olofkMaybe it won't fire without interrupts enableed?09:36
shornehmm, lets see whats in verilog09:36
olofkttcr_run is 009:38
shornethats not good09:39
olofkHmm... does & or | take precedence?09:39
olofkLine 7709:39
shorneim look at it09:39
shorneyour ttmr is 0x009:39
olofkYEs09:40
olofkoh wait09:40
shorneso first is false & !ttcr_match | false09:40
olofkIt should be 0xc000000009:40
olofkWhy09:40
olofkhmm09:41
shorneThe Tick Timer facility is enabled with TTMR[M].09:41
shorne(from spec)09:41
olofkI got this line in the code or1k_mtspr(OR1K_SPR_TICK_TTMR_ADDR, 0xc0000000);09:41
olofkBut still spr_ttmr is 0 in the simulation09:41
olofkhmm.. in the waveform there is only one access to that register, but I'm writing to it three times09:43
shornehmm09:44
shornewhat abbout trying to use OR1K_SPR_TICK_TTMR_MODE_SET()09:46
shornenot sure where its defined, but see it in some of stekern's code09:47
shorneits in libgloss, so you can use it09:48
shornehttps://github.com/openrisc/newlib/blob/or1k/libgloss/or1k/include/or1k-sprs.h09:50
olofkoh.. I was too quick09:51
olofkThe real accceses came much later. The one I saw was just some part of the board init09:51
shorneah right09:53
olofkFinally! I think it's running now09:53
olofkhttp://06cdd72458f7edf8.paste.se/09:54
shornevery short09:55
olofkThat's basically what I need to implement a usleep09:55
shorneI need some usleep10:03
olofk:)10:04
wallentoolofk, you have to be careful though not to interfere with any other timer11:15
SMDwrkguys, I've noticed, that in or1200 specification there is no system register that holds cycles count after start. Is there a reason for not having it?11:17
SMDwrkI think it would be cool to have it: you can easily measure time(in cycles) passed between reading.11:19
SMDwrkAnd if we have PMU where current freq is set, we could calculate time in seconds11:19
olofkSMDwrk: Another option would also be to just use a separate core for this. pros: We don't need to write it in the spec. cons: It won't be completely portable16:37
olofkBut I agree that it could be useful to have16:42
jiahi all, how can I make or1k linux support ATA-IDE drive?20:09
shornejia, do you know how to communicate with hardware on the wishbone bus?21:43
jiano, and, does it neessery? I mean in Linux code.21:47
shornewell, there are multiple layers 1. making sure the ata-ide is connected to the or1k cpu via hardware/fpga/wishbone bus21:48
shornethen 2, defining the controller+address in your device tree21:49
shornethen 3, linux driver21:49
shornefor 1, if you are doing fpga you would want your ide controller to be a wishbone slave, and setup the address (in a wishbone conf) i.e.21:51
shornehttps://github.com/openrisc/orpsoc-cores/blob/master/systems/de0_nano/data/wb_intercon.conf21:51
shornefor 2. YOu would define in the device tree, i.e.21:52
shornehttps://github.com/openrisc/linux/blob/master/arch/openrisc/boot/dts/de0_nano.dts21:52
jiafor 3, there is already done by linux.  Is it right.21:53
jiathank you very much for this example!21:53
shornefor linux code you can look at example drivers, i.e. opencores,uart16550-rtlsvn105  opencores,i2c-ocores21:53
shornewell, ide is supported by linux21:53
shornebut if you look at an ata drivers, they are build for a specific chip21:55
shornehttps://github.com/openrisc/linux/tree/master/drivers/ata21:56
shorneI dont know if we ahve a wishbone compatible ata core21:56
shorneor the linux driver for it21:56
jiaoh21:57
shornei.e. something like this21:57
shornehttp://www.hitechglobal.com/IPCores/SATADevice.htm21:57
jiahttps://github.com/skristiansson/linux/blob/openrisc/arch/openrisc/boot/dts/simple_smp.dts21:57
jiaIt has a ata-generic21:57
shorneah, cool then its there21:58
jiaI just need a linux with IDE to test qemu-or3221:58
shorneI see the driver is this one linux/drivers/ata/pata_of_platform.c22:01
shorneI guess if that is the case qemu-or32 would support ata, so you dont need step 1 from above22:02
jiaI'm working on make qemu-or support it22:02
shorneI see, cool well you will need to build linux with the device tree definition as in the simple_smp.dts (uncommented)22:04
shornethen in qemu you would simulate the ata controller be listining to address writes at 9e00000022:04
shornereg = <0x9e000040 0x3022:04
shorne0x9e000078 0x10>;22:04
jiaI add the ata into or1ksim.dts :)22:05
jiaand then, need I modify anything else in Linux?22:06
jiasome code, or make menuconfig stuff?22:06
shornethen you will need to enable that driver in ata driver selection "OpenFirmware platform device PATA support" right?22:07
shorneand "Generic platform device PATA support"22:07
jiaI'm asking for here, you can tell I don't Linux :cry22:08
shorneyeah, need to select those in menuconfig22:08
jiaI'm trying, thank you, you are so kind22:10
shorneI can see in or1ksim/sim.cfg, 0x9e000000 ATA disc22:18
shornethat matches dts22:18
jiamake menuconfig in or1k linux, there is no ATA option...22:21
shornemay be hard to find22:23
shornechecking...22:23
shorne1. at the top level enable "Enable the block layer"22:25
jiadone22:26
jiaOh, got!22:26
shorne2. in Device Drivers --> Serial ATA and Parallel ADA drivers (enable)22:26
jiaGeneric platform devices PATA support22:27
shorneyes, then after that is enabled you can see OpenFirmware ...22:27
jiaOpenFirmware platform device PATA support22:27
jiamay I ask, which toolchain you use?22:29
jiaI can't build busybox or linux using or1k-linux-musl-22:29
shorneI have been using newlib22:30
shorneor1k-elf-22:31
jiacan newlib toolchain build busybox? I tried last night, failed on busybox-1.2422:31
shorneI havent tried, but the openrisc linux has busybox binaries already included22:31
shorneso I never bothered with it, do you need something extra?22:32
jiaHumm... not sure I'm using linus's repo.22:33
jiakernel built, build busybox and make image file, now22:35
shorneAh, you might be a bit better off using https://github.com/openrisc/linux22:38
shorneyou probably will be ok though, but it has busybox already included22:38
jiawe make it a ATA-IDE, so now, busybox should be on the "disk" that is a sys.img file;)22:41
shorneright, doesnt have to be in the initrd img22:51
shorneolofk: For wb_builder the perl script I have found seems to be the only think available.  Is there another option for generating wishbone interconnects?22:54
shorneI created a fork of freecores and fixed some bugs here https://github.com/stffrdhrn/wb_builder22:55
shorneahrgg "THIS FILE IS AUTOGENERATED BY wb_intercon_gen"23:10
shorneolofk: I found it23:11
--- Log closed Sat Sep 10 00:00:05 2016

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