| --- Log opened Fri Sep 09 00:00:03 2016 | ||
| olofk | Any other way to sleep for an amount of time with a bare-metal or1k program? | 05:20 |
|---|---|---|
| olofk | aha. Maybe I should try the timer functions in libgloss | 05:31 |
| olofk | wallento: You know these things, right? How do I use the timer to implement a simple usleep? | 05:34 |
| wallento | I will tell you if you update http://openrisc.io/newlib/tutorial.html afterwards ;) | 05:35 |
| olofk | I found this! :) http://openrisc.io/newlib/docs/html/group__or1k__timer.html | 05:35 |
| wallento | shit, you already found it | 05:37 |
| wallento | :-D | 05:37 |
| wallento | I think you wanna use the timer handler stuff | 05:37 |
| wallento | the default handler just increases ticks | 05:37 |
| wallento | so either you wait for the ticks to increment or set your handler | 05:38 |
| olofk | Waiting seems easier. It's just a single thread | 05:38 |
| olofk | So, init, enable and then read get_ticks until I'm happy with the value there? | 05:39 |
| olofk | The good thing is that I can just do a quick test program and run it in icarus to check | 05:40 |
| olofk | With more or less the same RTL as in HW | 05:40 |
| olofk | (except for mem controller. I replaced that with a simulated Avalon memory instead) | 05:40 |
| wallento | yes, that should work | 05:43 |
| olofk | Works fine | 05:55 |
| olofk | or maybe not | 06:10 |
| olofk | ...or maybe | 06:12 |
| olofk | Aha. Looks like I set the timer frequency too high, so it never got time to do anything before the next interrupt | 06:16 |
| stekern | doesn't it read the ticks directly from the timer? | 06:17 |
| olofk | I haven't really figured out all about the timer yet | 06:19 |
| olofk | wallento: What on earth is this good for? while (ticks == or1k_timer_get_ticks()) { } | 06:20 |
| olofk | It looks like this will only exit when ticks == 0 | 06:22 |
| stekern | it will exit when ticks != or1k_timer_get_ticks() | 06:23 |
| olofk | oh, right | 06:23 |
| olofk | I suck a tC | 06:24 |
| olofk | at C | 06:24 |
| olofk | and writing | 06:24 |
| stekern | stop sucking tC | 06:24 |
| olofk | :) | 06:24 |
| stekern | ;) | 06:24 |
| olofk | Looks like or1k_timer_get_ticks only return 0 | 06:25 |
| olofk | Maybe I should run it on the board instead | 06:26 |
| olofk | I can see that the ttcr register is moving in the waveform, but still nothing from get_ticks | 06:36 |
| stekern | I repeat, does the get_ticks read the ticks directly from the timer (+ the accumulated periods)? | 06:39 |
| stekern | I seem to remember that there was something odd with get_ticks like that, but I might well remember wrong | 06:40 |
| stekern | right, "ticks" is number of accumulated periods | 06:57 |
| stekern | maybe that's fine for you? but I recall that I needed finer granularity than that for something sometime | 07:19 |
| wallento | I think you can set the granularity too | 07:28 |
| wallento | http://openrisc.io/newlib/docs/html/group__or1k__timer.html#gaf760867d2f9d04f0c101c4c4975b0616 | 07:29 |
| wallento | void or1k_timer_set_period (uint32_t hz) | 07:29 |
| stekern | yes, but then you increase the interrupt frequency | 07:29 |
| stekern | and I wanted to run without the timer exception enabled | 07:29 |
| stekern | afair | 07:29 |
| wallento | ah, Isee | 07:31 |
| olofk | I still don't get it | 07:46 |
| olofk | I love the heartbeat parameter that I added to vlog_tb_utils | 07:53 |
| olofk | usesoc sim zem4310 --elf-load=timer.elf --timeout=30000000 --heartbeat=1000000 | 07:53 |
| olofk | f | 07:54 |
| olofk | Tells me I have time to get a coffee before the sim is finished :) | 07:54 |
| wallento | the timer generates interrupts and the default handler increments the ticks | 08:12 |
| wallento | you can set your own handler and change the frequency of interrupts | 08:13 |
| wallento | or turn it to one shot etc. | 08:13 |
| olofk | http://22d649fe06df7da7.paste.se/ | 08:13 |
| olofk | I run this for 30us | 08:14 |
| olofk | If I got this right, I should get a interrupt every 20us | 08:14 |
| olofk | Also, if I raise the frequency to 100000 it stops working | 08:15 |
| olofk | I just looked quickly at the VCD, but I think it doesn't have time to finish the interrupt before a new one comes in | 08:15 |
| olofk | The CPU runs at 50MHz | 08:15 |
| wallento | thats 1000 cycles | 08:23 |
| wallento | if that is the issue you probably have to build something yourself with a one-shot timer then | 08:24 |
| wallento | ah, wait | 08:24 |
| wallento | or set your own handler and count up to a your value in the handler | 08:24 |
| wallento | when you reach it, disable the timer | 08:24 |
| wallento | but it will not be precise then | 08:25 |
| wallento | because you are reaching the limits | 08:25 |
| wallento | if it needs to be more precise you should probably use it as stekern described | 08:25 |
| olofk | It doesn't have to be very precise. Just want to sleep for a while, say 500 us | 08:29 |
| olofk | But I still don't get what's wrong | 08:29 |
| olofk | With or1k_timer_init(50000), the tick should increse every 20us, right? | 08:30 |
| olofk | The high frequency I'm using now is just so I don't have to simulate forever | 08:31 |
| olofk | Or did you mean that 50000 is also too high? | 08:31 |
| _franck___ | I don't know how the timer works in openrisc but in general if I have to do that on a microcontroller, I set timer count frequency to 1µs, preset its value to 20 and while(!timer_expired_flag); | 08:41 |
| _franck___ | you don't need interrupt overhead | 08:41 |
| olofk | True | 08:44 |
| olofk | So we should probably add a function to get the ttmr value too | 08:47 |
| olofk | And for now I'll read it out directly from the reg | 08:48 |
| olofk | ttcr I mean | 08:49 |
| olofk | Much better! | 08:52 |
| olofk | ticks = or1k_mfspr(OR1K_SPR_TICK_TTCR_ADDR); | 08:52 |
| olofk | Hmmm.. but why does it stop at 1955 ? | 08:53 |
| olofk | Maybe I should read up on the timer in the spec | 08:57 |
| wallento | I second that ;) | 08:59 |
| olofk | ok, almost | 09:03 |
| olofk | ahh.. enabling the timer without an interrupt handler is of course bad | 09:13 |
| olofk | But I don't need interrupts | 09:13 |
| olofk | Ahhh!!! How to I make the damn timer start? | 09:25 |
| shorne | or1k_timer_restore(timerstate); | 09:26 |
| shorne | now sure what you are doing though | 09:26 |
| shorne | https://github.com/openrisc/tutorials/blob/master/sw/timer/timer.c | 09:26 |
| olofk | Right now I'm just trying to figure out how this thing works | 09:27 |
| _franck___ | olofk: http://git.pengutronix.de/?p=barebox.git;a=blob;f=arch/openrisc/lib/clock.c;h=a171214a5379f7719ae26698689b359128432fb3;hb=HEAD#l25 | 09:28 |
| olofk | I don't want any interrupts. I just want to set the timer to 0 and start counting | 09:28 |
| _franck___ | I might remember I needed mtspr(SPR_TTMR, SPR_TTMR_CR | 0xFFFFFF); or it didn't start to count | 09:28 |
| olofk | Both are set to 0 in my test code | 09:30 |
| olofk | Both ttmr and ttcr | 09:30 |
| olofk | And then I set the mode to 0x3, which should be free-running clock | 09:30 |
| shorne | you want to se TTMR_M to start incrementing ? | 09:32 |
| olofk | Yes. I'm setting it to mode 0x3 now | 09:33 |
| shorne | when TTMR_M TTCR keept counting forever | 09:33 |
| olofk | or1k_mtspr(OR1K_SPR_TICK_TTMR_ADDR, 0xc0000000); | 09:33 |
| olofk | And before that I set both TTMR and TTCR to 0 | 09:34 |
| shorne | so you can just read TTCR every few cycles | 09:34 |
| shorne | but TTCR is not incrementing? | 09:35 |
| olofk | exactly | 09:35 |
| shorne | what about UPR_TTP? | 09:35 |
| olofk | ? | 09:35 |
| shorne | timer exists? | 09:35 |
| shorne | UPR[TTP] specifies whether | 09:35 |
| shorne | or not the tick timer facility is present | 09:35 |
| shorne | (from spec) just a sanity check | 09:35 |
| olofk | I have gotten it to work, but not with my code | 09:35 |
| shorne | I see | 09:35 |
| olofk | Maybe it won't fire without interrupts enableed? | 09:36 |
| shorne | hmm, lets see whats in verilog | 09:36 |
| olofk | ttcr_run is 0 | 09:38 |
| shorne | thats not good | 09:39 |
| olofk | Hmm... does & or | take precedence? | 09:39 |
| olofk | Line 77 | 09:39 |
| shorne | im look at it | 09:39 |
| shorne | your ttmr is 0x0 | 09:39 |
| olofk | YEs | 09:40 |
| olofk | oh wait | 09:40 |
| shorne | so first is false & !ttcr_match | false | 09:40 |
| olofk | It should be 0xc0000000 | 09:40 |
| olofk | Why | 09:40 |
| olofk | hmm | 09:41 |
| shorne | The Tick Timer facility is enabled with TTMR[M]. | 09:41 |
| shorne | (from spec) | 09:41 |
| olofk | I got this line in the code or1k_mtspr(OR1K_SPR_TICK_TTMR_ADDR, 0xc0000000); | 09:41 |
| olofk | But still spr_ttmr is 0 in the simulation | 09:41 |
| olofk | hmm.. in the waveform there is only one access to that register, but I'm writing to it three times | 09:43 |
| shorne | hmm | 09:44 |
| shorne | what abbout trying to use OR1K_SPR_TICK_TTMR_MODE_SET() | 09:46 |
| shorne | not sure where its defined, but see it in some of stekern's code | 09:47 |
| shorne | its in libgloss, so you can use it | 09:48 |
| shorne | https://github.com/openrisc/newlib/blob/or1k/libgloss/or1k/include/or1k-sprs.h | 09:50 |
| olofk | oh.. I was too quick | 09:51 |
| olofk | The real accceses came much later. The one I saw was just some part of the board init | 09:51 |
| shorne | ah right | 09:53 |
| olofk | Finally! I think it's running now | 09:53 |
| olofk | http://06cdd72458f7edf8.paste.se/ | 09:54 |
| shorne | very short | 09:55 |
| olofk | That's basically what I need to implement a usleep | 09:55 |
| shorne | I need some usleep | 10:03 |
| olofk | :) | 10:04 |
| wallento | olofk, you have to be careful though not to interfere with any other timer | 11:15 |
| SMDwrk | guys, I've noticed, that in or1200 specification there is no system register that holds cycles count after start. Is there a reason for not having it? | 11:17 |
| SMDwrk | I think it would be cool to have it: you can easily measure time(in cycles) passed between reading. | 11:19 |
| SMDwrk | And if we have PMU where current freq is set, we could calculate time in seconds | 11:19 |
| olofk | SMDwrk: Another option would also be to just use a separate core for this. pros: We don't need to write it in the spec. cons: It won't be completely portable | 16:37 |
| olofk | But I agree that it could be useful to have | 16:42 |
| jia | hi all, how can I make or1k linux support ATA-IDE drive? | 20:09 |
| shorne | jia, do you know how to communicate with hardware on the wishbone bus? | 21:43 |
| jia | no, and, does it neessery? I mean in Linux code. | 21:47 |
| shorne | well, there are multiple layers 1. making sure the ata-ide is connected to the or1k cpu via hardware/fpga/wishbone bus | 21:48 |
| shorne | then 2, defining the controller+address in your device tree | 21:49 |
| shorne | then 3, linux driver | 21:49 |
| shorne | for 1, if you are doing fpga you would want your ide controller to be a wishbone slave, and setup the address (in a wishbone conf) i.e. | 21:51 |
| shorne | https://github.com/openrisc/orpsoc-cores/blob/master/systems/de0_nano/data/wb_intercon.conf | 21:51 |
| shorne | for 2. YOu would define in the device tree, i.e. | 21:52 |
| shorne | https://github.com/openrisc/linux/blob/master/arch/openrisc/boot/dts/de0_nano.dts | 21:52 |
| jia | for 3, there is already done by linux. Is it right. | 21:53 |
| jia | thank you very much for this example! | 21:53 |
| shorne | for linux code you can look at example drivers, i.e. opencores,uart16550-rtlsvn105 opencores,i2c-ocores | 21:53 |
| shorne | well, ide is supported by linux | 21:53 |
| shorne | but if you look at an ata drivers, they are build for a specific chip | 21:55 |
| shorne | https://github.com/openrisc/linux/tree/master/drivers/ata | 21:56 |
| shorne | I dont know if we ahve a wishbone compatible ata core | 21:56 |
| shorne | or the linux driver for it | 21:56 |
| jia | oh | 21:57 |
| shorne | i.e. something like this | 21:57 |
| shorne | http://www.hitechglobal.com/IPCores/SATADevice.htm | 21:57 |
| jia | https://github.com/skristiansson/linux/blob/openrisc/arch/openrisc/boot/dts/simple_smp.dts | 21:57 |
| jia | It has a ata-generic | 21:57 |
| shorne | ah, cool then its there | 21:58 |
| jia | I just need a linux with IDE to test qemu-or32 | 21:58 |
| shorne | I see the driver is this one linux/drivers/ata/pata_of_platform.c | 22:01 |
| shorne | I guess if that is the case qemu-or32 would support ata, so you dont need step 1 from above | 22:02 |
| jia | I'm working on make qemu-or support it | 22:02 |
| shorne | I see, cool well you will need to build linux with the device tree definition as in the simple_smp.dts (uncommented) | 22:04 |
| shorne | then in qemu you would simulate the ata controller be listining to address writes at 9e000000 | 22:04 |
| shorne | reg = <0x9e000040 0x30 | 22:04 |
| shorne | 0x9e000078 0x10>; | 22:04 |
| jia | I add the ata into or1ksim.dts :) | 22:05 |
| jia | and then, need I modify anything else in Linux? | 22:06 |
| jia | some code, or make menuconfig stuff? | 22:06 |
| shorne | then you will need to enable that driver in ata driver selection "OpenFirmware platform device PATA support" right? | 22:07 |
| shorne | and "Generic platform device PATA support" | 22:07 |
| jia | I'm asking for here, you can tell I don't Linux :cry | 22:08 |
| shorne | yeah, need to select those in menuconfig | 22:08 |
| jia | I'm trying, thank you, you are so kind | 22:10 |
| shorne | I can see in or1ksim/sim.cfg, 0x9e000000 ATA disc | 22:18 |
| shorne | that matches dts | 22:18 |
| jia | make menuconfig in or1k linux, there is no ATA option... | 22:21 |
| shorne | may be hard to find | 22:23 |
| shorne | checking... | 22:23 |
| shorne | 1. at the top level enable "Enable the block layer" | 22:25 |
| jia | done | 22:26 |
| jia | Oh, got! | 22:26 |
| shorne | 2. in Device Drivers --> Serial ATA and Parallel ADA drivers (enable) | 22:26 |
| jia | Generic platform devices PATA support | 22:27 |
| shorne | yes, then after that is enabled you can see OpenFirmware ... | 22:27 |
| jia | OpenFirmware platform device PATA support | 22:27 |
| jia | may I ask, which toolchain you use? | 22:29 |
| jia | I can't build busybox or linux using or1k-linux-musl- | 22:29 |
| shorne | I have been using newlib | 22:30 |
| shorne | or1k-elf- | 22:31 |
| jia | can newlib toolchain build busybox? I tried last night, failed on busybox-1.24 | 22:31 |
| shorne | I havent tried, but the openrisc linux has busybox binaries already included | 22:31 |
| shorne | so I never bothered with it, do you need something extra? | 22:32 |
| jia | Humm... not sure I'm using linus's repo. | 22:33 |
| jia | kernel built, build busybox and make image file, now | 22:35 |
| shorne | Ah, you might be a bit better off using https://github.com/openrisc/linux | 22:38 |
| shorne | you probably will be ok though, but it has busybox already included | 22:38 |
| jia | we make it a ATA-IDE, so now, busybox should be on the "disk" that is a sys.img file;) | 22:41 |
| shorne | right, doesnt have to be in the initrd img | 22:51 |
| shorne | olofk: For wb_builder the perl script I have found seems to be the only think available. Is there another option for generating wishbone interconnects? | 22:54 |
| shorne | I created a fork of freecores and fixed some bugs here https://github.com/stffrdhrn/wb_builder | 22:55 |
| shorne | ahrgg "THIS FILE IS AUTOGENERATED BY wb_intercon_gen" | 23:10 |
| shorne | olofk: I found it | 23:11 |
| --- Log closed Sat Sep 10 00:00:05 2016 | ||
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