IRC logs for #openrisc Tuesday, 2016-09-06

--- Log opened Tue Sep 06 00:00:59 2016
mor1kx[mor1kx] wallento pushed 1 new commit to master:
mor1kxmor1kx/master 736b625 Stefan Wallentowitz: Fix verilog mode template04:37
mor1kx[mor1kx] spacemonkeydelivers closed pull request #38: Introducing Performance Counter Unit (master...master)
wallentoanyone ever faced by the baremetal toolchain building GOT into object files?10:52
vidyaHello all, Is it possible to toggle a GPIO pin other than the LEDs using a C code in OR1K running on DE0 Nano board?11:04
ZipCPUHold on ... let me take a peek ...11:08
ZipCPULooks like it has 8 GPIO I/O's, and 4 GPIO inputs ...11:10
ZipCPUControlled by two separate GPIO controllers ...11:11
vidyaHow did you figure it out? In the verilog files?11:12
ZipCPUYou can find the pins those GPIO controllers control in the data/pinmap.tcl file within the system core.11:13
vidyaOk. What is the base address that I have to use in the C code to toggle the pin?11:13
ZipCPUIf you have fusesoc installed, which I do, I find a copy of that core in .local/share/orpsoc-cores/systems/de0_nano/...11:13
ZipCPULet's see ... that would be in the wb_intercon.v file ...11:14
ZipCPUor maybe not ...11:15
vidyaI checked the LED or UART C code both of which specify a base address. I suppose I have to get separate base address to drive a GPIO pin on board?11:16
ZipCPUYeah ... there it is.  Thank's _franck__!  The first GPIO is at 0x9100_0000, and the second at 0x9200_0000!11:18
ZipCPUSo that gives you the base addresses of the two GPIO peripherals.11:18
ZipCPUControl the first, and you can control 8 I/O pins to be either inputs, or outputs, and you can set their values.11:19
vidya_frank_ thanks a lot. One more question to access general GPIO pin I will have to use 0x9200_0000 address right?11:19
ZipCPUThere are two GPIO controllers.  One controls 8 gpio0_io pins, which are both inputs and outputs, the other controls 4 input pins.11:19
ZipCPUYou can find that piece of the configuration in the rtl/verilog/orpsoc_top.v file.11:20
vidyaI want to get an output from the board so that should be gpio0?11:20
ZipCPUThe 0x9100_0000 address gives you access to the gpio0_io pins.11:20
ZipCPUThe 0x9200_0000 address gives you access to the gpio1_i (input only) pins.11:21
vidyaso other than the LED pins the other pin descriptions are not there in qsf11:21
vidyaSo I have to add them manually?11:21
vidyaI'm not too sure of the flow actually11:21
ZipCPUHelp me out for a moment, do those 12 pins connect to anything you are interested in controlling?11:22
ZipCPUBear with me, I don't have a de0_nano board ... but I can see that the board has 8 LED's and 4 dip-switches.11:23
ZipCPUIt makes sense, then that the GPIO controller would drive these two.11:23
ZipCPUSince the GPIO controller can only control 8-bits, you may wish to ... connect another four bits to GPIO controller #1,11:24
ZipCPUor create a third GPIO controller.11:24
vidyaI want to use the GPIO controller to use some other IO pins on board11:25
vidyaother than what is default pins11:25
ZipCPUI guess it depends on how hard you want to work at it.11:26
ZipCPUOne method would be to use the LED controller (GPIO0) to also control your pins, and then just adjust the LED's to output what's going on on the pin you are interested in.11:27
ZipCPUAnother method might be to integrate a third GPIO controller.11:27
vidyaI was thinking something similar to the first method you mentioned11:28
vidyainstead of blinking the LED can I drive another pin on board? How to do this?11:28
ZipCPU1) You'll need to "connect" the pin to the design, and create a new toplevel port within orpsoc_top.v11:29
ZipCPU2) You'll need to create a pin assignment for your pin, in a fashion similar to line 850 that assigns to gpio0_in[i].11:30
ZipCPU3) You'll also want to "disconnect" the pin from the current port (line 850), and set the read input to your new port.11:31
ZipCPUSo, let's call your port "user_io".  You would then ...11:31
vidyaOk let's suppose I declared the port in the top ad output and the pin assignment also done. How the LED code will access this top port?11:32
ZipCPUassign user_io = gpio0_dir[PIN] ? gpio0_out[PIN] : 1'bz;11:32
ZipCPUand adjust the assign gpio0_in[PIN] so that11:32
ZipCPUgpio0_in[PIN] = gpio0_dir[PIN] ? gpio0_out[PIN] : user_io;11:32
ZipCPU(where PIN is the pin number, 0-7, as defined by the GPIO controller.  You pick which one ...)11:33
vidyafor output from the board , assign user_io =  gpio0_out[PIN]; is this right?11:41
vidyaCan add just this line?11:41
ZipCPUSure, why not?11:41
ZipCPUYou might want to adjust it so it handles the direction pin of the GPIO port as well, but sure!11:42
vidyaYeah, right! I think I have an idea now. I will try it on board and check if it works. Thanku very much <ZipCPU>11:43
ZipCPUMy pleasure.11:43
ZipCPUvidya: Were you the individual that just wrote to the openrisc mailing list on librecores as well?  Or does someone else still need their question answered?12:28
vidyaYeah one of my lab mate asked that question.12:33
ZipCPU|LaptopOkay, I think I've got all the logic in place for a pipelined wishbone master to axi slave bus converter.14:55
ZipCPU|LaptopI opened up a new project for it, and now I just need to figure out how to test it.14:56
olofkZipCPU|Laptop: You could use my wb_bfm and a AXI memory for the slave15:08
ZipCPU|LaptopCan I verilate your wb_bfm?15:09
olofkZipCPU|Laptop: No, it's behavioural verilog15:11
ZipCPU|LaptopHmm ... I'm going to struggle verilating an AXI memory too, aren't I?15:11
olofkI've been thinking of doing a synthesizable one, that could be used for verilator15:11
olofkNo, you can do the memory pretty easily15:12
olofkLooking around orpsoc-cores, I see that there is the axi_mem_if_DP component from the Pulpino guys.15:15
olofkThere's a axi_mem_if_SP component in that repo too. That could probably be used right away15:15
olofkI guess15:15
ZipCPU|LaptopOkay, I see it in orpsoc, but it'll take me another step to look it up.15:16
olofkUnfortunately there isn't any stand-alone testbench for that core15:16
* ZipCPU|Laptop laughs.15:16
ZipCPU|LaptopHow often is there?15:16
olofkYeah, I know :/15:17
olofkOk, the axi_mem_if_SP is a bridge between AXI and a SRAM interface15:18
olofkI'll see if I can throw something together15:18
olofkI have a feeling that I already have something somewhere15:19
ZipCPU|LaptopThe core includes the capability (should it work) to reorder out of order responses.15:19
olofkProbably not15:20
ZipCPU|LaptopThat should handle any problems folks have had with pipelined translations in the past.15:20
olofkNever seen reordering being used in AXI actually15:20
ZipCPU|LaptopThat's fine--its parameterizable, and can be turned off.15:20
olofkOr was that not a question? Did you mean that axi_mem_if_SP does reodering?15:22
ZipCPU|LaptopNo, I mean that the pipelined wishbone master to AXI slave translater I just built will reorder things if necessary.15:22
ZipCPU|LaptopThe logic to do it was simple enough, although it will cost an extra clock delay on the return path.15:23
olofkHow on earth do you handle that on the wishbone side? There's no info on the wb bus to tell which transaction that a data is attached to15:23
ZipCPU|LaptopCreate a FIFO.  Clear the fifo whenever the strobe is low.15:23
ZipCPU|LaptopUse the FIFO head as the transaction ID for the AXI.15:24
ZipCPU|Laptop(fifo head pointer, that is)15:24
ZipCPU|LaptopIt becomes a one-up counter in the AXI interface.15:24
ZipCPU|LaptopAXI responses come back with their transaction ID, so use that to fill in the return FIFO in an out of order fashion if necessary.15:24
olofkAh ok. But then you can't handle bursts, right? Only single accesses15:24
ZipCPU|LaptopYou mean, AXI bursts?15:25
ZipCPU|LaptopI mapped everything to single accesses.15:25
ZipCPU|LaptopAs long as it'll let me do multiple single accesses in a row, I'm golden.15:25
ZipCPU|Laptop*Every* access is the last one in its burst.15:25
olofkThat probably works15:26
ZipCPU|LaptopWe'll see what happens when the core meets ... something real as a test case.15:27
olofkIf you use an event-based sim instead of verilator, you will probably have a higher chance of getting something to play with15:28
ZipCPU|LaptopHey, this is neat: I just requested an open cores project for this core, and it already came back approved!15:29
ZipCPU|LaptopThat usually takes a day or so ...15:29
olofkLike in worst case using ISE or Vivado to generate a memory core with an AXI interface15:29
ZipCPU|LaptopBut I can drive it so nicely from Verilator ... I can have my CPU run the interface even ...15:30
olofkYeah. That would help a lot of course15:30
olofkIf you can run axi_mem_if_SP in verilator, coupled with a simple SRAM component that would solve the slave side15:30
olofkNot sure if there are any usable WB master BFMs however15:31
ZipCPU|LaptopRunning WB from a C++ test rig within Verilator isn't that hard.15:31
ZipCPU|LaptopIt's actually pretty easy.15:31
--- Log closed Wed Sep 07 00:00:00 2016

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