| --- Log opened Sun Sep 04 00:00:56 2016 | ||
| mithro | ZipCPU|Laptop: litedram -> https://github.com/enjoy-digital/litedram - DDR3, DDR2, DDR and SDRAM controller | 00:37 |
|---|---|---|
| andrzejr | mithro, is it better than Xilinx's DDR controller? | 04:43 |
| andrzejr | it still relies on encrypted primitives (serdes, phase interpolator) | 04:47 |
| andrzejr | what is the difference between litex and migen? (or what was the reason to fork migen?) | 04:50 |
| olofk | andrzejr: I don't think you can get around using those primitives | 07:22 |
| olofk | But If I understand correctly, the controller is technology agnostic, with only the phy specific to the FPGA | 07:22 |
| olofk | And with a DFI interface between them, which is a standardized interface for these sort of things | 07:22 |
| andrzejr | olofk, thanks, I didn't know about DFI. That makes sense | 14:58 |
| andrzejr | I wonder why Xilinx doesn't use it (not that I'm surprised) | 14:58 |
| shorne | oh, man, I wasted like 2 weeks trying to figure out what was wrong with my de0 nano/tool chain | 18:00 |
| shorne | I couldnt even get hello world to run on it | 18:00 |
| shorne | (hello world) should display on the serial console. In the end I move the serial lines to new pins and it worked | 18:01 |
| shorne | I think the old pins got static damage | 18:01 |
| --- Log closed Mon Sep 05 00:00:57 2016 | ||
Generated by irclog2html.py 2.15.2 by Marius Gedminas - find it at mg.pov.lt!