| --- Log opened Mon Aug 29 00:00:47 2016 | ||
| SMDhome1 | stekern: I've just noticed that in your dhrystone code all printfs are commented out. If you just add printf(%d, Int_1_loc), the result becomes significantly worse. | 03:12 |
|---|---|---|
| SMDhome1 | Could it be that gcc removes Int_1_loc computation while noone uses its result? | 03:12 |
| stekern | SMDhome1: maybe | 05:01 |
| stekern | I've only used that dhrystone test to make comparisons between changes (and between or1200 and mor1kx) | 05:02 |
| SMDwrk1 | stekern: ok, thanks | 05:03 |
| ZipCPU | stekern: If you've used dhrystone to make comparisons between or1200 and mor1kx, do you remember what the results were? | 07:52 |
| stekern | not more than mor1kx got better results | 08:15 |
| ZipCPU | stekern: That should be sufficient, as I'm working with mor1kx. | 08:32 |
| ZipCPU|Laptop | You know, we need to have a discussion one of these days about wishbone and AXI. | 16:16 |
| ZipCPU|Laptop | Personally, I've fallen in love with wishbone. It's simple. It's easy to use--or at least I've made it so. | 16:17 |
| ZipCPU|Laptop | It can also be amazingly fast. | 16:17 |
| ZipCPU|Laptop | Here's the problem: As long as Xilinx makes it so that you must use their memory controller, and their memory controller only supports AXI ... | 16:17 |
| ZipCPU|Laptop | It becomes harder to use wishbone. | 16:17 |
| ZipCPU|Laptop | As I understand, AXI offers a 3-clock I/O cycle for one data word, or a multi-clock I/O cycle for 256 ... bytes is it? | 16:19 |
| ZipCPU|Laptop | Wishbone offers everything in between. | 16:19 |
| ZipCPU|Laptop | Especially wishbone pipeline. | 16:21 |
| kc5tja | It allows 1-cycle single-beat transfers if you have memories fast enough. | 17:45 |
| ZipCPU | Which: wishbone or AXI? | 17:57 |
| ZipCPU | I mean, wishbone allows single-beat transfers and it is adaptable to whatever speed your memory (or other peripheral) can handle. | 17:57 |
| kc5tja | That's what I'm talking about. | 18:10 |
| ZipCPU | See ... that's some of my frustration with AXI. Wishbone is much more flexible. | 18:12 |
| kc5tja | I've never used, nor have I ever wanted to use, AXI. | 18:12 |
| kc5tja | I've always used Wishbone. | 18:12 |
| kc5tja | I'm pretty sure the only thing keeping Wishbone off of people's list of preferred buses is that (1) ARM doesn't and will never use it, (2) most commercial FPGA vendors are licensees of ARM, and that costs a *lot* of money. ARMs use AXI, and so it makes sense to re-use that bus interface for peripherals, and (3) most people are still aware only of some early predecessor to B3, and otherwise don't understand B3 and B4's capabilities. | 18:15 |
| kc5tja | But, Xilinx and Altera's appeal to authority virtually guarantees second-class status to Wishbone for anything resembling a professional design. | 18:15 |
| ZipCPU | Doesn't RISC-V use AXI? | 18:16 |
| kc5tja | It's more accurate to say that Rocket and BOOM use a compatible subset of their own design. Mine will use Wishbone. Most other designs, like picorv32, use some proprietary bus intended for minimum implementation complexity. | 18:18 |
| ZipCPU | So here's my pain: I need a wishbone controlled memory interface for DDR3. I can try to map AXI to wishbone, but I will lose a lot of capability. | 18:18 |
| ZipCPU | At least, that approach would give me the MIG DDR3 controller. | 18:19 |
| ZipCPU | (Can you sense some frustration here?) | 18:19 |
| kc5tja | MIG? | 18:19 |
| ZipCPU | Xilinx: Memory Interface Generator. | 18:19 |
| kc5tja | What capabilities are you going to lack? | 18:19 |
| ZipCPU | My problem is: MIG will roughly double my access time, and I have no reason to believe MIG will maintain the ability to stream/pipeline to the DDR3. | 18:19 |
| ZipCPU | I'd like to be able to pipeline from 1 to N words, stalled only by any need to refresh the memory. | 18:20 |
| kc5tja | Streaming is the *only* way to transfer data to an SDRAM interface, is it not? I can't fathom why they wouldn't use AXI's burst-mode transfers. | 18:20 |
| ZipCPU | So ... I like wishbone. A lot. B4/pipelined, it's just about perfect for any application. | 18:22 |
| ZipCPU | It's just ... taking a *lot* of work to get this memory controller running on the hardware. | 18:22 |
| ZipCPU | It's not clear that I'll be successful. | 18:23 |
| ZipCPU | But if I can get this controller working ... I'll have hand-tuned performance that will beat anything a generator-builds-all circuit can do. | 18:26 |
| mor1kx | [mor1kx] kraziant opened pull request #39: Add ORFPX32 commands at monitor trace (master...master) https://github.com/openrisc/mor1kx/pull/39 | 22:58 |
| --- Log closed Tue Aug 30 00:00:08 2016 | ||
Generated by irclog2html.py 2.15.2 by Marius Gedminas - find it at mg.pov.lt!