| --- Log opened Wed Aug 24 00:00:39 2016 | ||
| SMDhome1 | another stupid question: if I run fusesoc w/ verilator sim, where should I look for std{out,err}? I can't find anything | 02:12 |
|---|---|---|
| SMDhome1 | build/mor1kx-generic/sim-verilator/verilator.out.log is empty | 02:24 |
| SMDhome1 | olofk: could you give me a hint? | 10:07 |
| ZipCPU | SMDhome1: What's up? Is this the Verilator question from the night before? | 10:13 |
| SMDhome1 | ZipCPU I'm strugling to find verilator output | 10:13 |
| ZipCPU | Can you point me to a source code directory, so I can take a peek? | 10:13 |
| SMDhome1 | ZipCPU I guess this one is what gets compiled: orpsoc-cores/systems/mor1kx-generic/bench/verilator/tb.cpp | 10:14 |
| ZipCPU | (The one repository I didn't download last night ....) | 10:15 |
| SMDhome1 | you could just run fusesoc init | 10:15 |
| ZipCPU | What do I need to do first ... I don't have fusesoc installed? | 10:16 |
| SMDhome1 | Firstly install fusesoc: clone repo, then make pip install fusesoc, then choose dir and run "fusesoc init" there | 10:17 |
| ZipCPU | Wow --- that's pretty cheesy. The tb.cpp bench has no output. | 10:17 |
| SMDhome1 | I don't know how this thing got verilated( | 10:18 |
| SMDhome1 | I'm more like a sw guy that have interest in hw( | 10:18 |
| ZipCPU | No, it's a valid Verilator code, it's just that the CPU is not connected to any input/output. | 10:18 |
| SMDhome1 | fusesoc sim --sim=verilator mor1kx-generic --elf-load=bla | 10:18 |
| SMDhome1 | but this could fail due to wrong path to mor1kx src | 10:19 |
| ZipCPU | Ok, I've cloned fusesoc. But if I cd into that directory and do "make pip install" I just get errors. | 10:20 |
| SMDhome1 | sec | 10:20 |
| SMDhome1 | sudo pip install fusesoc | 10:20 |
| SMDhome1 | https://github.com/olofk/fusesoc check "quick start" | 10:20 |
| ZipCPU | Ok ... working from there. | 10:21 |
| SMDhome1 | ZipCPU I'm going to be afk for a couple of hours but I hope to get back to you and answer your questions | 10:21 |
| ZipCPU | Not a problem. I'll be crying in my milk in the meantime over what's going on with this memory controller I'm working on. | 10:22 |
| SMDhome1 | ZipCPU Btw, do you have lots of experience w/ xilinx memory controllers? | 10:22 |
| ZipCPU | All the wrong kind of experience it seems. | 10:23 |
| ZipCPU | I've written one SDRAM controller, and I'm now trying to write a DDR3 SDRAM controller. | 10:23 |
| ZipCPU | I've been at it for a couple of weeks now. | 10:23 |
| ZipCPU | Nothing works in the hardware ... yet. (Hence crying in my milk ...) | 10:23 |
| SMDhome1 | ZipCPU my task is rather simple: I have a board w/ spartan6 and ddr2 mem connected to it. So I want to get standart xilinx mem controller working/ | 10:24 |
| SMDhome1 | Too pity I don't have irc on my phone to continue chatting( | 10:24 |
| ZipCPU | I think I have all of the references you might need/want, but the one thing I do not have is anything currently working. | 10:24 |
| SMDeeepc | have I missed anything? | 11:38 |
| ZipCPU | Welcome back SMDeeepc! Anything particular that you are concerned about missing? | 11:58 |
| ZipCPU | opencores.com has changed hands ... | 11:58 |
| SMDeeepc | I still wonder how to get stdout of verilated fusesoc: need to obtain dhrystone results | 12:01 |
| ZipCPU | Well let's start with the first/obvious question: does the mor1k-generic core have a stdout port ... a UART perhaps? | 12:02 |
| SMDeeepc | I think so: running it w/ icarus does print to stdout | 12:04 |
| ZipCPU | Really ... ? | 12:10 |
| ZipCPU | (Back at keyboard now ...) | 12:10 |
| ZipCPU | I don't see anything useful in mor1kx-generic/bench/verilog/ or bench/verilator ... | 12:14 |
| ZipCPU | Ouch. Looks like the only peripheral exposed from the top level is the JTAG. | 12:17 |
| ZipCPU | Hmnmm ... rtl/verilog/orpsoc_top.v has connections for a UART, srx_pad_i and stx_pad_o, that aren't connected. | 12:20 |
| ZipCPU | If these could be exported as top level pins, then the XuLA2-LX25SoC uartsim.cpp module could be plugged in. | 12:21 |
| ZipCPU | That would give you input and output via a serial port from your simulation. | 12:21 |
| ZipCPU | wallento: I'm trying to build gcc for or1k, and ... getting hung up. Can you help me with the configure options? | 12:40 |
| ZipCPU | I'm using "../or1k-gcc/configure --with-gas --prefix=${INSTALL_BASE}/cross-tools --exec-prefix=${INSTALL_BASE}/cross-tools | 12:46 |
| ZipCPU | --target=or1k-elf --host=x86_64-cross-linux-gnu --with-sysroot=${INSTALL_BASE} --with-build-sysroot=${INSTALL_BASE} | 12:47 |
| ZipCPU | --with-lib-path=${INSTALL_BASE}/tools/lib --with-local-prefix=${INSTALL_BASE}/usr | 12:48 |
| ZipCPU | I get quite a ways into the build, until I get to a "or1k-elf-gcc: command not found" error. | 12:48 |
| kc5tja | One of these days, I need to learn Verilator. | 12:50 |
| kc5tja | For that matter, I need to get it to actually build. | 12:50 |
| wallento | ZipCPU: you get it in this build already? | 12:56 |
| wallento | I tend to suggest checking ${INSTALL_BASE}/cross-tool/bin is in your $PATH | 12:56 |
| ZipCPU | wallento: Gosh. That was obvious. Thanks! | 13:45 |
| ZipCPU | Ok, I made it until stdio.h wasn't found. Now to go looking for that ... | 13:54 |
| wallento | I never built with sysroot, so I suppose it may be related to that | 13:54 |
| wallento | what are you building it for, baremetal or Linux? | 13:55 |
| ZipCPU | Yes. ;) I seem to do all my work on baremetal, but it would be fun to have a Linux distro as well. Would it make sense to start with newlib? | 13:55 |
| ZipCPU | My immediate goal is simple to run dhrystone. | 13:56 |
| wallento | oh, well, there newlib is sufficient | 14:02 |
| wallento | have you tried building with the tutorial? | 14:02 |
| wallento | http://openrisc.io/newlib/building.html | 14:02 |
| ZipCPU | Ahh ... No I haven't. Nice. Thanks! | 14:02 |
| --- Log closed Thu Aug 25 00:00:41 2016 | ||
Generated by irclog2html.py 2.15.2 by Marius Gedminas - find it at mg.pov.lt!