| --- Log opened Sun Aug 21 00:00:35 2016 | ||
| kc5tja | Initial tests of SMG are panning out. Just implemented state machine for RISC-V load and store (albeit w/out illegal insn detection) and it's taking up all of a whopping 31 logic cells. | 02:07 |
|---|---|---|
| kc5tja | Yeah, I have to think that "case statements considered harmful" for FPGA state machine design. | 02:07 |
| SMDhome1 | kc5tja: so instead of case(insn) at decode stage you suggest to use smth like isAdd = CheckAdd(insn) and pass this wires further? | 02:41 |
| SMDhome1 | now I'm thinking I've said smth stupid | 02:45 |
| bandvig | I've got a off-topic question about "git". | 11:46 |
| bandvig | As far as I understand, I can crate branch on my local PC, I can commit into the branch, I can merge into the branch from other branches, I can switch my working copy across branches. | 11:47 |
| bandvig | However, if I don't push my branch into remote it continue stay "local" branch. Am I right? | 11:47 |
| kc5tja | SMDhome1: I actually use AND-OR logic explicitly instead of having it inferred by Verilog. | 15:36 |
| kc5tja | SMDhome1: So, a single match-response "on"-clause in my domain-specific language looks like this: | 15:36 |
| kc5tja | SMDhome1: [on [A B ~C ["D[4:1]" 4'b0010]] W X Y Z] | 15:37 |
| kc5tja | SMDhome1: This in turn compiles to something not unlike the following Verilog: | 15:37 |
| kc5tja | SMDhome1: wire match001 = A & B & ~C & D[4:1] == 4'b0010; | 15:37 |
| kc5tja | SMDhome1: wire output001 = match001 ? 1 : 0; // This bizarre statement gets optimized by Verilog during synthesis. | 15:38 |
| kc5tja | SMDhome1: wire output002 = match001 ? 1 : 0; | 15:38 |
| kc5tja | SMDhome1: wire output003 = match001 ? 1 : 0; // in case you're wondering, these are intermediate terms for asserting W X Y and Z. | 15:38 |
| kc5tja | SMDhome1: wire output004 = match001 ? 1 : 0; | 15:39 |
| kc5tja | SMDhome1: assign W = ... | output001 | ... ; // other assertion rules are logically-ORed here too. | 15:39 |
| kc5tja | SMDhome1: assign X = ... | output002 | ...; | 15:39 |
| kc5tja | SMDhome1: assign Y = ... | output003 | ...; | 15:39 |
| kc5tja | SMDhome1: assign Z = ... | output004 | ...; | 15:39 |
| kc5tja | If I'd used a compound form to assign X a specific value, then obviously the intermediate wire term for that would have the value I provide instead of defaulting to just 1. | 15:40 |
| kc5tja | So, basically, my SMG tool converts a truth-table into an AND-OR network not unlike what you'd find in a pre-programmed PLA chip. | 15:41 |
| kc5tja | The reason for doing all this is it gives me total, unequivocal control over how the FPGA's LUTs are utilized. Since Yosys and Xilinx ISE infer a bunch of ancilliary logic to preserve algorithmic integrity of the Verilog code, which is something I definitely don't want, encoding this logic using Verilog's default constructs actually wastes FPGA resources. | 15:43 |
| ZipCPU | olofk: Have you seen the binutils discussion list recently? They're looking for comments on a change that would affect the OR1K back end ... | 22:08 |
| ZipCPU | Message is from Alan Modra, subject "R_OR1K_GOTOFF_* relocations" | 22:17 |
| --- Log closed Mon Aug 22 00:00:36 2016 | ||
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