| --- Log opened Wed Jul 20 00:00:47 2016 | ||
| ZipCPU | olofk: Are you up for a fusesoc question? | 10:43 |
|---|---|---|
| olofk | ZipCPU: Always :) | 15:20 |
| ZipCPU | olofk: I've been trying to figure out how to answer darkzihard's question on OpenCores. | 15:41 |
| ZipCPU | I looked up the ucf file as distributed by Digilent, and the jtag isn't connected to the PMOD at all. | 15:42 |
| ZipCPU | This leaves me wondering, what is the jtag_tap module that he's referring to, and what capabilities does that module have? | 15:43 |
| olofk | I have been meaning to get back to him, but haven't had the time | 15:44 |
| olofk | For the Atlys port we use one of the PMOD connectors to break out the JTAG connection, since Digilent uses their stupid idiotic proprietary JTAG over USB transport so we can't use the uUSB connection other than to download the bitstream | 15:45 |
| olofk | Which means that a separate JTAG adapter has to be used and connected to the pmod port | 15:45 |
| olofk | It's really the same thing on the Terasic Altera boards, but in that case, the USB Blaster protocol has been reverse engineered, so we can connect with OpenOCD | 15:46 |
| olofk | I periodically ping Digilent about this to see if they can just release their stupid protocol | 15:46 |
| olofk | I know that for some Digilent boards, people have gotten around this by flashing the USB controller with custom firmware, but that only works for some boards | 15:47 |
| olofk | The fun part is that in those cases they have flashed it with a firmware that implements the Altera USB Blaster protocol instead, as there is an OpenOCD driver for that :) | 15:48 |
| ZipCPU | Hmm ... fascinating. So the PMOD does become a JTAG connector, ... but just for the virtual chip within the FPGA? | 16:03 |
| olofk | No, jtag_tap is a complete verilog-based JTAG controller | 16:11 |
| ZipCPU | But ... what does it control? The FPGA? Or something within the FPGA? | 16:12 |
| olofk | So it will be PC->(JTAG dongle)->PMOD->(FPGA pins)->jtag_tap->adv_debug_sys->(CPU+memory) | 16:12 |
| ZipCPU | So why isn't that controlling the virtual chip that is within the FPGA? | 16:12 |
| ZipCPU | The (CPU+memory) that is instantiated in logic? | 16:13 |
| olofk | Yse | 16:13 |
| olofk | The OpenRISC in this case | 16:13 |
| ZipCPU | Ok, got it. | 16:13 |
| olofk | The hard JTAG controller in the chip is connected to a USB bridge on the board. We can't access that one | 16:13 |
| ZipCPU | That's what I thought. | 16:14 |
| ZipCPU | What controller would you then use to access it? Did you say OpenOCD? | 16:14 |
| olofk | OpenOCD is the JTAG proxy we usually use on the PC side | 16:20 |
| olofk | It has a bunch of drivers, including one that opens a socket, so we can run JTAG against a running simulation | 16:20 |
| olofk | I don't own a physical JTAG dongle however, so I have no recommendations for that | 16:22 |
| olofk | Think there are some cheap ones with OpenOCD drivers | 16:22 |
| kc5tja | Dumb question: What is OpenOCD? | 16:23 |
| olofk | kc5tja: It's a program that connects to your physical JTAG dongle on one side and opens up a bunch of sockets on the other | 16:24 |
| olofk | So to run gdb against a target you start openocd which opens a GDB remote protocol port, and then connect gdb to that | 16:25 |
| kc5tja | Ahh, I see. On Chip Debugger. | 16:26 |
| olofk | But I usually use the direct interface (which is on another port) so I can telnet into localhost:4444 and start/stop the CPU, read/write memory and download elf files | 16:28 |
| olofk | Very handy | 16:28 |
| olofk | There's also a possibility to tunnel a UART through another socket. It works fine in polled mode with adv_debug_sys, but there is some problem when Linux turns on the interrupts | 16:29 |
| olofk | Getting that to work would be great, since we can then run JTAG+UART through the same connection on the boards that support it | 16:29 |
| olofk | So all in all, getting the Digilent boards to use this system too would be really nice | 16:30 |
| olofk | hmm... has anyone had any success lately with using fusesoc to get cores from opencores? | 17:13 |
| olofk | I wonder if they have removed the orpsoc user account | 17:13 |
| ZipCPU | Now wouldn't that just be icing on the cake. Are you guys really at that much odds with each other? | 17:14 |
| olofk | It's not really a conflict, but we always had different opinions on getting access to the repos without registering on the site | 17:15 |
| olofk | As a compromise, we decided to create a separate user that fusesoc could use to get access to the repos | 17:16 |
| olofk | But that guy on the forum was having problems, and now I'm having problems too | 17:16 |
| ZipCPU | Can you "log in" to the site using the fusesoc username and password? | 17:16 |
| olofk | good question | 17:17 |
| olofk | Nop | 17:17 |
| olofk | e | 17:17 |
| olofk | Not sure it's a full user account though | 17:17 |
| olofk | This is awkward. Most of the cores are already migrated to github, but there was a new one I wanted to add | 17:18 |
| ZipCPU | Which core are you missing? | 17:19 |
| olofk | There is of course the option to make it possible to supply your own account when running FuseSoC, but I need to implement that, and it's a bit of a hassle for users | 17:19 |
| olofk | I just read about a sha256 VHDL core and wanted to show how easy it is to add FuseSoC support | 17:19 |
| olofk | Kind of lost it's point when I can't access the core though :) | 17:19 |
| ZipCPU | Sigh. | 17:20 |
| olofk | Took me about one minut to write the core and then some a few more minutes to run the testbench through three different simulators | 17:20 |
| --- Log closed Thu Jul 21 00:00:48 2016 | ||
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