IRC logs for #openrisc Wednesday, 2016-07-20

--- Log opened Wed Jul 20 00:00:47 2016
ZipCPUolofk: Are you up for a fusesoc question?10:43
olofkZipCPU: Always :)15:20
ZipCPUolofk: I've been trying to figure out how to answer darkzihard's question on OpenCores.15:41
ZipCPUI looked up the ucf file as distributed by Digilent, and the jtag isn't connected to the PMOD at all.15:42
ZipCPUThis leaves me wondering, what is the jtag_tap module that he's referring to, and what capabilities does that module have?15:43
olofkI have been meaning to get back to him, but haven't had the time15:44
olofkFor the Atlys port we use one of the PMOD connectors to break out the JTAG connection, since Digilent uses their stupid idiotic proprietary JTAG over USB transport so we can't use the uUSB connection other than to download the bitstream15:45
olofkWhich means that a separate JTAG adapter has to be used and connected to the pmod port15:45
olofkIt's really the same thing on the Terasic Altera boards, but in that case, the USB Blaster protocol has been reverse engineered, so we can connect with OpenOCD15:46
olofkI periodically ping Digilent about this to see if they can just release their stupid protocol15:46
olofkI know that for some Digilent boards, people have gotten around this by flashing the USB controller with custom firmware, but that only works for some boards15:47
olofkThe fun part is that in those cases they have flashed it with a firmware that implements the Altera USB Blaster protocol instead, as there is an OpenOCD driver for that :)15:48
ZipCPUHmm ... fascinating.  So the PMOD does become a JTAG connector, ... but just for the virtual chip within the FPGA?16:03
olofkNo, jtag_tap is a complete verilog-based JTAG controller16:11
ZipCPUBut ... what does it control?  The FPGA?  Or something within the FPGA?16:12
olofkSo it will be PC->(JTAG dongle)->PMOD->(FPGA pins)->jtag_tap->adv_debug_sys->(CPU+memory)16:12
ZipCPUSo why isn't that controlling the virtual chip that is within the FPGA?16:12
ZipCPUThe (CPU+memory) that is instantiated in logic?16:13
olofkThe OpenRISC in this case16:13
ZipCPUOk, got it.16:13
olofkThe hard JTAG controller in the chip is connected to a USB bridge on the board. We can't access that one16:13
ZipCPUThat's what I  thought.16:14
ZipCPUWhat controller would you then use to access it?  Did you say OpenOCD?16:14
olofkOpenOCD is the JTAG proxy we usually use on the PC side16:20
olofkIt has a bunch of drivers, including one that opens a socket, so we can run JTAG against a running simulation16:20
olofkI don't own a physical JTAG dongle however, so I have no recommendations for that16:22
olofkThink there are some cheap ones with OpenOCD drivers16:22
kc5tjaDumb question: What is OpenOCD?16:23
olofkkc5tja: It's a program that connects to your physical JTAG dongle on one side and opens up a bunch of sockets on the other16:24
olofkSo to run gdb against a target you start openocd which opens a GDB remote protocol port, and then connect gdb to that16:25
kc5tjaAhh, I see.  On Chip Debugger.16:26
olofkBut I usually use the direct interface (which is on another port) so I can telnet into localhost:4444 and start/stop the CPU, read/write memory and download elf files16:28
olofkVery handy16:28
olofkThere's also a possibility to tunnel a UART through another socket. It works fine in polled mode with adv_debug_sys, but there is some problem when Linux turns on the interrupts16:29
olofkGetting that to work would be great, since we can then run JTAG+UART through the same connection on the boards that support it16:29
olofkSo all in all, getting the Digilent boards to use this system too would be really nice16:30
olofkhmm... has anyone had any success lately with using fusesoc to get cores from opencores?17:13
olofkI wonder if they have removed the orpsoc user account17:13
ZipCPUNow wouldn't that just be icing on the cake.  Are you guys really at that much odds with each other?17:14
olofkIt's not really a conflict, but we always had different opinions on getting access to the repos without registering on the site17:15
olofkAs a compromise, we decided to create a separate user that fusesoc could use to get access to the repos17:16
olofkBut that guy on the forum was having problems, and now I'm having problems too17:16
ZipCPUCan you "log in" to the site using the fusesoc username and password?17:16
olofkgood question17:17
olofkNot sure it's a full user account though17:17
olofkThis is awkward. Most of the cores are already migrated to github, but there was a new one I wanted to add17:18
ZipCPUWhich core are you missing?17:19
olofkThere is of course the option to make it possible to supply your own account when running FuseSoC, but I need to implement that, and it's a bit of a hassle for users17:19
olofkI just read about a sha256 VHDL core and wanted to show how easy it is to add FuseSoC support17:19
olofkKind of lost it's point when I can't access the core though :)17:19
olofkTook me about one minut to write the core and then some a few more minutes to run the testbench through three different simulators17:20
--- Log closed Thu Jul 21 00:00:48 2016

Generated by 2.15.2 by Marius Gedminas - find it at!