IRC logs for #openrisc Thursday, 2016-06-30

--- Log opened Thu Jun 30 00:00:17 2016
wallentoSMDhome: Yes, the stuff is still there01:17
wallentowe need to migrate this information to the github repo for the spec01:17
SMDhomeZipCPU that's an extention01:34
-!- Netsplit *.net <-> *.split quits: a0u, Empyrium05:08
-!- Empyrium_ is now known as Empyrium05:21
ZipCPUSMDhome: Thanks!  That's what I was looking for.  Does that mean that a double precision hardware floating point unit exists?07:46
ZipCPUSMDhome: Are the 64-bit integers and vector instructions also optional extensions?07:48
olofZipCPU: Yes they are07:50
olofMost or1k implementations only implement ORBIS32 (the 32-bit integer parts)07:51
ZipCPUThe ZipCPU isn't all that different--lots of configurability, although I will admit that or1k appears to be much more so.  ;)07:51
ZipCPUSo here's what I'm up to: I'm trying to put together a simplified comparison between a variety of soft cores.  You can see how far08:00
ZipCPUI've gotten at, in the ZipCPU project: trunk/doc/orconf.pdf.08:00
ZipCPUFeel free to let me know if I've in anyway misrepresented, or misaccounted, any platform listed there.08:00
ZipCPU(I'm comparing: Nios (2), uBlaze, ECO32, RISCV, and OpenRISC ...)08:01
olof219 instructions? Is that for real? :)08:05
ZipCPUYeah.  That was my thought when I went through and counted.08:05
ZipCPUIn the end, I counted pages in the architecture document, and noted that every page had an instruction on it.08:06
olofok, looks like ORBIS32 has around 100 instructions08:11
olofMost of them seem to be valid for ORBIS64 as well08:11
olofThen there's about 30 FP instructions08:12
ZipCPUHow should I count them?  Are instructions listed in the openrisc-arch-1.1-rev0.pdf more than once?08:12
olofAnd around 90 vector instructions. No wonder that no one has implemented the vector parts yet :)08:15
olofI think a fair comparasion would be to count the ones in orbis32.08:16
olofBut it's hard. Did you count the vector instructions for uBlaze?08:16
ZipCPUI can do that.  Should I list the others in a range?  For example, 100-219?08:17
ZipCPUDo you know how to identify microblaze vector instructions from within the rest of the set?08:18
olofSorry, no. Haven't done uBlaze stuff for quite some tim08:18
olofIt's up to you how you want to present them, but for OpenRISC you can say that the core ISA is ~100 instructions, FP an additional 30, and vectors 90 extra08:20
ZipCPUI count 99 ORBIS32/ORBIS64 instructions pages, so I'll use 99 as the lower end.08:20
olofI guess it's the same for RISC-V08:20
olofWhich parts of the RISC-V ISA did you use?08:20
olofNo, sorry08:20
olofI mean IMA08:20
olof...I think08:20
olofInteger, Mul/div and atomic. That's roughly the same as ORBIS3208:21
ZipCPUJust the bare basic instruction set--the minimal set that needed to be implemented.08:21
olofaha. Then you can cut out some more for openrisc. mul, div, sra, ff1, fl1 and cust1-6 are for example not required08:21
olofAlso not l.swa and l.lwa08:21
olofActually, I think only those with "Instruction Class ORBIS32 I" at the bottom of the page are required08:23
ZipCPUOkay, that gets you down to 48, if I've counted right.  (I missed where that instruction class was noted, I looked all over the top of the page for it ...)08:25
olofI think I counted ~48 class one instructions08:25
olofYeah, it was a bit hard to find. I just searched for "class", and hoped to find something :)08:26
ZipCPUAnd here I didn't think the process had any "class"  (sorry, bad joke ...).08:27
olof...moving on...08:29
ZipCPUOkay, so the number is 48 (minimal), 99+30+vector (full)08:29
ZipCPUAnd the floating point and vector are extensions, as must be the other 51 basic instructions.08:30
olofSounds about right08:31
olofAny of you globetrotters who know if I will be able to use a phone bought in the US when I'm back in Sweden?08:35
ZipCPUDon't look at me--I'm not much of a globetrotter, so I wouldn't know.08:37
ZipCPUHmm ... 48,99+30+91 doesn't make sense if I don't similarly count the RISC-V optional instruction sets.08:39
ZipCPUI might just label RISCV as 50(min), and OpenRISC then as 48(min).08:40
olofI guess that minimum is the slightly more important number in this comparasion08:43
ZipCPUYes.  Especially for what I am trying to accomplish.08:44
ZipCPUI mean, consider, the OR1K spec outlines over 500+ special purpose registers (gasp!).  Again, I tried to pick the minimum there as well.08:46
wallentoolof: yes, mostly ;)08:46
wallentoit should be quad band and not be bought at an operator08:47
wallentothan it should work08:47
olofI was thinking of retiring my Nokia 105 and by some Android phone. Thought it might be cheaper in the US08:49
olofOh... I never realized that the OpenOCD server at port 4444 is a full TCL interpreter08:50
olofThat could had saved me from a LOT of typing over the years08:53
wallentoolof: I think its not much cheaper09:06
wallentoespecially now with the weakened euro09:07
olofwallento: We're not a euro country09:13
olofBut still. The dollar is stronger than in a while09:14
olofoh.. I'm not buying stuff in dollars right now. It was worse than I thought09:15
wallentoah, right, forgot09:15
wallentobut technology is evenly priced in us, eu and japan now I think09:16
olofYeah, I guess you need to go to Switzerland is you want to get really high prices09:17
olofInto the darkness again.10:43
olofReally wish they would fix my home internet connection soon10:43
-!- Netsplit *.net <-> *.split quits: fotis2, wallento, nurelin17:45
--- Log closed Fri Jul 01 00:00:18 2016

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