IRC logs for #openrisc Monday, 2016-05-30

--- Log opened Mon May 30 00:00:29 2016
jeremybennettshorne: I haven't been following the whole conversation. Is it that you want to upstream GDB with the Or1ksim integration.05:29
jeremybennettI have no problem with my or1ksim work going to the FSF (I have the necessary FSF paperwork in place). However most of Or1ksim predates me, so you'd need those authors' permission as well.05:30
LoneTechI'm tempted to try getting libgomp openmp 4 or Cray Chapel offloading to run on the Epiphany05:52
olofjeremybennett: It's the other way around. We want to push gdb with the regular sim backend06:24
olofTo avoid the or1ksim dependency for the upstream code06:24
jeremybennettolof: Much better idea. In which case you don't need to worry about or1ksim.06:38
olofjeremybennett: I think that shorne mainly wanted your blessing for removing the or1ksim stuff when we push it upstream06:46
jeremybennettolof: shorne: That's fine by me06:50
olofthanks jeremybennett06:51
shornejeremybennett: its that we now have 2 simulators in gdb 1. the cgen based simulator completely housed in gdb, 2. the or1ksim which depends on the externel libsim provided by or1ksim.07:52
shorneWe were thinking that to upstream gdb we would go with the internal cgen version, that way gdb doesnt have gnu external dependencies07:53
shorneolof: thanks for already explaining07:54
shornejeremybennett: thanks I missed your reply at first07:54
stolarwallento: shorne: or anyone know how to switch off multiplier ( ~ Unit responsible for multiplication) in or1ksim or openrisc? I think it is related with Arithmetic Logic Unit.11:36
tariq786can anyone tell me what is the bare minimum openrisc i need to run linux on top of it?12:37
-!- tariq786 is now known as kaaliakahn12:38
GeneralStupidkaaliakahn: one ?12:41
olofkkaaliakahn: As I said yesterday, you need a CPU, memory controller and UART12:43
kaaliakahnOlofk: where can i get these 3 things or should i make my own12:44
olofkIf you have an Atlys board, we have a preconfigured system you can build with FuseSoC12:44
kaaliakahnolofk: I want to do bottom up approach12:44
kaaliakahnI don't have an idea about RISC architecture. I want to learn it as well.12:45
kaaliakahnso please suggest a custom approach such that after following it, I can contribute like you guys are doing12:45
olofkkaaliakahn: Then I would recommend that you start with some simpler system that won't necessarily run Linux12:45
kaaliakahnbut first i need to learn this giant system12:45
kaaliakahnyes sure12:45
kaaliakahnrunning linux can be the next step12:46
kaaliakahnwhere do i get started then12:46
olofkIf you just want to study the CPU, you can run simulations with small compiled programs12:46
olofkYou can do that either on simulated RTL code, or in the C simulator12:47
kaaliakahnso lets break it down bottom up and make sure it is doable12:47
kaaliakahnso here is what i am thinking.12:47
kaaliakahnstudy cpu, simulate cpu, cpu + mem controller, cpu + mem controller simulation, cpu + mem controller + uart, simulation of the former12:48
olofkYou will need some kind of memory connected to the CPU so that the CPU can load and run a program12:49
olofkSo the minimum configuration would be cpu + mem controller12:49
olofkThis is basically the mor1kx-generic SoC that you can find in the FuseSoC library12:50
kaaliakahnolofk: sure. I am thinking to make a tutorial along the way so beginners like me can follow that12:50
olofkIt is meant to be a bare minimum simulation environment12:50
kaaliakahnor is there a tutorial like this from baby steps to giant steps12:50
olofkkaaliakahn: Absolutely agree. We are aware of the lack of tutorials to get started :/12:51
olofkBut we are trying to rectify this now
olofkIt's not that much yet though12:51
kaaliakahnI am happy to do that. But please help me get the momentum12:51
kaaliakahnso where do i find the cpu + mem controller?12:51
olofkIf you just need a memory controller for simulation, you can use this one
olofkAnd for the CPU we use mor1kx
olofkAnd if you want to see a top-level that binds it all together, I recommend that you take a look at the mor1kx-generic system here
olofkYou will need to download and install the toolchain to be able to compile your own programs too. Have you done that?12:54
kaaliakahnolofk: As you recall, I remained in the RTL only world12:54
kaaliakahnolofk: so please clarify a few things for me as they confuse a hell lot of me12:55
olofkah yes, right. There is a whole lot of software to this as well :)12:55
kaaliakahnok lets go one by one. You earlier wrote a few minutes ago12:55
kaaliakahn"If you just want to study the CPU, you can run simulations with small compiled programs. You can either do that on simulated RTL code or C simulator"12:56
kaaliakahnWhat i know and have done is RTL verilog with RTL test bench and thats it. For example CPU dut in verilog and its testbench in verilog as well12:57
olofkYep. We have that option12:57
kaaliakahnwhat does compiled program means in the context of cpu and what is C simulation?12:57
kaaliakahnhow do you explain this to a RTL guy who lived in RTL cave :)12:58
olofkLet me try :)12:58
olofkWhen you compile your code with the OpenRISC compiler, you get an executable file.12:59
olofkThis file can be run on a real OpenRISC system running in an FPGA or an ASIC13:00
olofkOr we can run it in an emulator13:00
olofkThe C simulator that I mentioned before is called or1ksim. It's an emulator (written in C) that can load an OpenRISC executable on your PC just as if it would be running on a real OpenRISC13:01
olofkBut we can forget about that for now, since what you're likely is interested in is running verilog simualations13:01
olofkQuestions so far? :)13:02
kaaliakahnok. It means there are two separate things. One is developing OpenRISC in RTL and one is developing applications that run on openRISC. Right? The former is purely RTL. The latter is C programming cross compiled with openrisc compiler. Correct?13:02
kaaliakahndid i use the term cross compiler correctly? :)13:03
olofkYes, you did :)13:03
kaaliakahnolofk: I am interested in both and that is the goal. First understand OpenRISC RTL then the compiler and then run the two together13:04
olofkSo now we want to run our cross-compiled program on the RTL code in a simulator such as modelsim or icarus13:04
kaaliakahnso lets now plan a tutorial that goes bottom up approach13:04
olofkSure. Understanding the compiler isn't something I would recommend though :)13:04
kaaliakahnhang on. I have a question13:05
kaaliakahnso you are recommending running cross compiled programs  on RTL code in Model Sim? How is it different from running a verilog testbench. I am wondering what would this simulation show?13:06
kaaliakahnand how do you interface cross compiled programs with RTL? assuming cross compiled program acts as Testbench for RTL?13:07
kaaliakahnI am not worried about compiler. It does what it is supposed to do GIGO (garbage in, garabage out)  :)13:08
olofkWhat we do in the testbench is that we preload a memory with an OpenRISC executable, and when we release the reset, the simulated CPU will start fetching instructions from that memory13:09
kaaliakahnok. So its like readmem kind of thing?13:10
olofkYes, more or less13:10
kaaliakahnok. I am good so far. Is this what you recommend as the first step?13:10
olofkBut with FuseSoC we can load an executable file directly into the testbench with some VPI magic13:10
olofkYes, I think that's a good first step13:11
olofkAnd the mor1kx-generic SoC that I pointed out before has all the facilities to do that for you13:11
olofkI somewhat expect that there will be  several things that could need some more explaining before you're up to speed13:12
kaaliakahnjust to confirm, it is this one   ??13:12
olofkThat's the CPU13:12
kaaliakahnbut dont you think, one needs to understand CPU and then the mem controller before going to generic SoC?13:14
kaaliakahnI am trying to come up with table of contents for the tutorial.13:14
kaaliakahnlike part 1, part 2, part 3, ...13:14
kaaliakahngoing from baby steps to giant steps13:15
SMDwrkkaaliakahn: ask wallento about tutorial13:15
olofkThe mor1kx-generic SoC is a basic SoC just for this kind of purpose13:15
olofkIt's not possible to run the mor1kx-generic SoC on real HW. Only in simulations13:15
kaaliakahnolofk: Where is the documenation for mor1kx-generic13:17
olofkBecause it uses a very basic memory controller that wouldn't be possible to implement in an FPGA13:17
olofkWell, here's the fun part. There isn't really any documentation13:17
kaaliakahnSMDwrk: tutorial on what specific topic that wallento might be able to help?13:18
olofkWhich sucks of course13:18
kaaliakahnolofk: wow13:18
SMDwrkask him, I don't know for sure13:18
SMDwrkI decided to read mor1kx code and let others do their soc magic13:19
kaaliakahnolofk: No worries. I will try to document it13:19
kaaliakahnguys you are doing amazing job in development but some what slacking in documentation13:19
SMDwrkas always13:20
SMDwrkkaaliakahn: speaking of documentation, what are you going to do? I mean which part of it13:20
kaaliakahnmay be i can chip in my 2 cens here13:20
olofkYeah, we're not proud of the situation :/13:20
kaaliakahnSMDwrk: I am going to understand how SoC works and document it for beginners13:20
kaaliakahnin a step by step manner13:21
kaaliakahnand that is what i was talking to olofk13:21
SMDwrkI'm going to deal with mor1kx rtl sources, make pipeline scheme and so on13:21
SMDwrkkaaliakahn: in that case you really should talk to wallento, IIRC he had same plans as you13:21
kaaliakahnSMDwrk: It seems you know the RTL source code13:22
kaaliakahnwhat does IIRC mean :)13:22
SMDwrkif i remember correctly13:22
kaaliakahnI am going to message him. But as you said you are going to make drawings of the pipeline.13:22
SMDwrkkaaliakahn: I'm struggling to know it)13:22
SMDwrkyep, that's my plan. But it relates only to cpu-core, not soc all in all13:23
kaaliakahnso we are in the same boat in a stormy weather ;)13:23
kaaliakahnare you talking about the mor1kx-generic-soc ?13:24
SMDwrkI use it to run my binaries, yes13:24
kaaliakahnwhat exactly are those binaries? I mean what programs?13:24
SMDwrkLet's say dhrystone. I use baremetal toolchain, dhrystone sources, compile it to elf and then run it on simulator13:26
kaaliakahnok. so benchmarks13:26
kaaliakahnok. I know my work to do13:27
kaaliakahncan you explain what is baremetal toolchain?13:27
SMDwrkI'm interested it perfomance mostly, so I'll try to improve mor1kx one13:28
SMDwrkCorrect me plz, but baremetal toolchain differs from linux one in c library, which is used.13:29
kaaliakahni think it differs in the compiler itself13:36
kaaliakahnit wont use gcc, it would use arm-gcc instead13:36
kaaliakahnas an example13:36
kaaliakahnthe answer is quite good13:37
SMDwrkFirstly we use cross-compilation: with given toolchain you compile binary file on x86 machine for orisk arch.13:38
SMDwrkThen with cross-compiler you can compile binary in elf format either for linux, or for baremetal usage.13:39
SMDwrkLet's say you use printf() in your c prog. In case of baremetal toolchain it will call printf implementation which will send data to the uart port, while using linux toolchain it will somehow use existing linux stdio13:40
SMDwrkSo the difference is, as I see it, in standart c library13:41
kaaliakahnyeah that is correct13:42
kaaliakahnbut remember compiler is also different as i said and its compiler's job13:42
SMDhomekaaliakahn: what's different? or1k-elf- and or1k-linnux-gnueabi-?14:49
stolarin this file: should be l_cust5 instruction, but there is no instruction like that. wtf?15:41
SMDhomestolar: try to add it16:39
SMDhomeDo we have up to 7 l.cust?16:39
stolarSMDhome: I add it and everything is fine16:41
SMDhomethen, I think, someone just forgot to add it. And since it's custom instruction noone really cared about it16:41
SMDhomestolar: what's your task? I wonder if you do this to study sim internals or this is real isa extention16:50
stolarIt's a part of project on my university ( wroclaw university of technology - POLAND)  from computere architecture course. I am studying computer science.17:08
stolarSMDhome: It isn't commercial, probably I will not publish result of my project17:10
stolarSMDhome: Currently I study or1ksim how it works etc. to pass subject + it is a real extension, probably nobody do this in the world. Topic: modulo instruction and residue number system17:15
stolarSMDhome: You can  read sth aboout my project in IRC logs  from e.g   First question i  ask on IRC 16th may 2016, nickname: stolar17:18
--- Log closed Tue May 31 00:00:31 2016

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