IRC logs for #openrisc Saturday, 2016-05-28

--- Log opened Sat May 28 00:00:26 2016
olofkshorne_: Good find. And strange behaviour03:16
olofkSorry that I haven't gotten back to your pull request. I'll try to do that today03:16
shorne_olofk: in the end I got it to be able to find gcc with some hacks.  But it tries to mmap the code into the host but it seems thats only available on linux.  So probably we dont want to support compile for now.05:09
olofkshorne_: Fair enough.06:46
wallentoshorne_: I pulled your request06:55
wallentosorry I was always thinking it will be amended with further fixes :)06:56
wallentothanks a lot, I very much appreciate your hard efforts!06:56
olofkwallento: There's a lot of merges in the tree now. Should we untangle this a bit before pushing upstream?06:56
olofkshorne_: I think you need to sign the fsf copyright paper also before we can push this upstream06:57
olofkHaven't done it myself, but there are plenty of other people here who knows what should be done06:57
wallentoolofk: yes of course06:57
wallentowe should rebase onto a single update06:57
wallentoor a few06:57
wallentowe did it with newlib too06:58
olofkah ok.06:58
wallentoyou just need to do a git diff master or1k from time to time06:58
wallentoto be really sure :)06:58
olofkHow does this travis integration on github work? Can I just add a .travis.yml to my repo, or do I need to register somewhere and let travis know that my project exists?07:40
wallentoolofk: you need to register08:02
wallentoat travis-ci.org08:02
wallentoThen browse your repos and those of the orgs08:03
wallentoand turn it on08:03
wallentothen in the settings you should turn on "only build when .travis.yml is present"08:03
wallentothats it08:03
wallentoI think you can register with Github OAuth08:04
wallentoyes, its Github authentication08:04
bandvigI've got a question which is regard to interaction DU and other CPU modules.09:43
bandvigIn particular. Could I made assumption that pipeline have to be stalled (by DU command) before DU-reading various SPR and GPR?09:43
tariq786hi There. I have a couple of basic questions for anyone to answer12:57
tariq786Q1) What is the difference between OpenRISC and OpenRISC Soc?12:59
tariq786or between OR1200 and ORPSOC?12:59
GeneralStupidi hope i'll tell you the right things.13:02
tariq786GeneralStupid: Please go ahead13:02
GeneralStupidOpenRISC is a Processor Architecture13:02
GeneralStupidan OpenRISC SoC is a Processor which can be actually used (because it will need things like the wishbone bus for example. The SoC is a complete processor with an OpenRISC Core)13:03
GeneralStupidOR1200 is one openrisc implementation, like mor1kx13:03
GeneralStupidORPSOC is the reference plattform (the reference openrisc SoC)13:04
tariq786GeneralStupid: When you say processor architecture, does it mean only ALU and Control logic?13:05
tariq786GeneralStupid: When you say SOC, it is ALU + control logic + peripherals? Am i correct?13:06
GeneralStupidi had some very nice documentation with nice diagrams ... but i dont find it right now13:12
GeneralStupidif you want to start i would recommend fusesoc to you13:13
tariq786where is fusesoc?13:13
tariq786GeneralStupid: Please correct my statements in green above if you think they are wrong13:14
GeneralStupidtariq786: i would say your right.13:14
tariq786GeneralStupid: I have seen somewhere people are running linux on top of OpenRISC. Is that possible?13:15
tariq786GeneralStupid: is it OpenRISC or ORPSOC?13:16
GeneralStupidi think you can say openrisc13:18
GeneralStupidyes it is possivle13:18
GeneralStupidµClinux afaik13:18
tariq786GeneralStupid: what make is possible to run linux on openrisc?13:19
GeneralStupidwhat do you mean?13:19
tariq786GeneralStupid: it is hard to sink in somehow :(13:21
tariq786GeneralStupid: So lets go thru this thought process13:22
tariq786GeneralStupid: what makes intel or AMD run linux13:22
tariq786GeneralStupid: Linux can be thought of as list of instructions and openRisc can be thought of as a processor that can execute that instructions13:23
tariq786GeneralStupid: does this analogy makes sense? or is incomplete or bogus?13:23
GeneralStupidlinux is a list of instructions14:15
GeneralStupidat last every program or software you run is "just" a list of instructions. An Operating System, too14:16
GeneralStupidbut that is not something which is particular with openrisc14:16
olofktariq786, GeneralStupid : A few corrections and clarifications15:09
olofkWhen we talk about OpenRISC we often mean "OpenRISC 1000", which is the specification15:10
olofkThe specification describes what each CPU instruction does and similar things15:10
GeneralStupidolofk: i thoight openrisct would be the specification15:12
olofkTo give a comparasion, x86 is another specification. There are tons of different CPUs (Intel Celeron, Atom, Core etc as well as CPUs from AMD, Cyrix and VIA) that all implement the x86 specification15:13
olofkYou can find the specification here
olofkThen we have the processor implementations, the actual CPU cores that implement the spec15:14
olofkThe original one was called or1200, but the one we mostly use nowadays is called mor1kx. There are also other implementations such as altor32, or10n and other15:14
olofkThere is also a javascript implementation ( that implements openrisc 1000 (or or1k as we call it), and a C simulator called or1ksim15:15
olofkThen we have the SoC part15:16
olofkDesktop CPUs still mostly have the CPU in a separate chip and then external chips for networking, usb, graphics and so on15:16
olofkBut in the embedded space (cell phones, appliances etc) this is usually all built into a single chip15:17
olofkHence the System on Chip (SoC)15:17
tariq786 olofk: Please excuse my ignorance. But i hope i can learn from you and then educate others15:17
tariq786 olofk: Thanks for the explanation15:18
olofkWe can put whatever we want in the chip, but early in OpenRISC development there was something called ORPSoC which was then OpenRISC Reference System on Chip15:18
olofktariq786: No worrries. Happy to explain15:18
tariq786 olofk: what is current ORPSoC called?15:18
olofkORPSoC consisted of the or1200 CPU + some chosen peripheral controllers such as a UART, memory controller and basic stuff15:18
tariq786 olofk: It seems it was similar to Amber,amber. Correct me if i am wrong15:19
olofktariq786: juliusb created orpsoc version 2 some years ago, and I started doing ORPSoCv3 some time later15:19
olofkBut both of these projects are dead now15:19
tariq786 olofk: why?15:19
olofkEven though orpsocv2 is still used15:19
olofkBecause I created something called FuseSoC instead15:20
tariq786 olofk: great. Why did you create this instead of Orpsoc315:20
olofkFuseSoC is created from a need that we saw in the OpenRISC community, but it has no dependency on OpenRISC. Therefore I didn't want OpenRISC in the name15:21
tariq786 olofk: did you create an RISC implementation from the scratch for fuseSoC?15:21
olofkI did it because I saw that I could use the FuseSoC project for all kinds of FPGA development, even though it didn't contain a CPU15:21
olofktariq786: No, neither FuseSoC nor ORPSoC has no real RTL code. It's just systems to bind together cores and create a SoC15:22
tariq786 olofk: should n't SoC have a CPU such as OpenRISC?15:23
olofkSo FuseSoC is basically a package manager15:23
olofkWell, I guess that most things that are called a SoC has a CPU inside, but there are plenty of other chips that has no CPU15:24
olofkSo to wrap it up, we now use FuseSoC to help us put together SoCs with OpenRISC and a bunch of peripherals15:24
olofkoh, and I draw that diagram you posted before :)15:24
olofkFrom myriadrf15:24
tariq786 olofk: please give examples of soc without cpu15:24
tariq786thats the last question15:25
tariq786ok later when you have time15:25
tariq786 olofk: I want to contribute to this open source work. How may i get started?15:25
tariq786 Anyone here to answer a few more questions?16:28
tariq786 What is the minimum RTL required to boot linux?17:07
tariq786 Can a single cycle (unpipelined) ALU + Control logic in RTL meet this requirement? I hope not?17:09
tariq786 If not, what are the essential components needed to boot linux off RTL? thanks for your patience17:09
olofktariq786: Starting with your last question, we have SoCs based on both mor1kx and or1200 that can boot Linux on several different FPGA boards17:11
olofkThe absolute minimum components you need are a CPU and a memory controller17:11
olofkYou probably won't get far without a UART as well17:12
olofkDo you have an FPGA board?17:12
tariq786 olofk: yes, digilentinc's SPartan 617:12
olofktariq786: Hmm... which one? Atlys, LX9 Microboard?17:13
olofkThey got several Spartan6-based boards :)17:14
tariq786hang on a minute17:14
GeneralStupidwhats about a de0 nano?17:15
GeneralStupidits pretty cheap17:15
tariq786I already have digilent's spartan 617:16
olofktariq786: Well then, you're in luck. We have a SoC implementation already for Atlys17:16
tariq786Olofk: Why i am going through this pain is so that i can contribute like you guys are doing. I am very much open source17:16
olofktariq786: We're happy to help out17:17
tariq786here is a snapshot of my 2 cents17:17
tariq786olofk: I don't have large scale or system level experience. That is why i am struggling with growing pains17:18
tariq786 olofk: and i thought to ask you for help17:19
tariq786 olofk: Here are a few more17:19
tariq786 olofk: Here is the board that i have17:22
olofktariq786: So, these are cores that you have already done?17:22
tariq786olofk: yes17:22
tariq786olofk: but you see, its not large scale or system level as i said earlier17:22
tariq786that is why i consider it only a small contribution17:23
olofktariq786: That's fine, and I think FuseSoC can be helpful here17:23
olofkWhat I want to do with FuseSoC is to create a large library of components that can be used by different implementations17:23
tariq786olofk: please explain more17:24
olofkThere are already ~100 cores available in the standard FuseSoC library17:24
tariq786can you give me a link so i can take a look at these 100 cores17:24
olofktariq786: You have any experience with software package management, such as rpm or deb packages?17:24
tariq786olofk: I have used them to install on Ubuntu and Fedora systems. Thats what i know17:25
olofktariq786: Well, think of FuseSoC as the equivalent, but for VHDL/verilog code. Instead of putting all your code in a single repository, you can more easily reuse existing code and only have what's unique for your project17:27
olofkSo you create a package description for your gcm-aes core, and other projects can depend on that17:27
olofkOr for your HDMI2Ethernet project, you can separate it into different cores, and then have a top-level project that depends on all the other parts17:28
olofkThat way other projects can also use the subcomponents17:28
tariq786olofk: that is more like coregen in Xilinx?17:29
olofktariq786: Yes, partly17:29
tariq786olofk: partly?17:29
olofkCoregen is only for Xilinx cores. FuseSoC currently handles Altera Quartus, Xilinx ISE and IceStorm for building FPGA binaries17:30
olofkCoregen also doesn't handle dependencies17:31
olofkAnd with FuseSoC, you can run your testbenches in different simulators17:31
tariq786olofk: is there a good time to discuss in detail tomorrow?17:32
tariq786olofk: How can i use my Atlys board to play with FuseSoC?17:33
tariq786gtg but catch you later17:34
olofktariq786: Not sure how much I'll be around tomorrow17:34
olofkBut get fusesoc from
olofkInstall it and run "fusesoc build atlys" to generate a OpenRISC SoC for your board17:35
olofktariq786: FYI, I just now created a basic core file for your gcm_aes project, so you can simulate it in FuseSoC17:39
olofkJust to get you an idea of how to make a core FuseSoC-compatible17:41
olofkJust tested it with four different simulators. Testbench seems to run fine in all of them, but it seems like I'm missing some exit criteria17:43
ZipCPU|Laptopolofk: I am currently in the process of building an SD-Card controller that will work with a SPI interface, as opposed to the normal SD interface.17:43
ZipCPU|LaptopIs there anything special that I will need to do in order to make it FuseSoC compatible?17:44
olofktariq786: This is what it looks lik
olofkZipCPU|Laptop: Just out of curiosity, why not reuse an existing one?17:45
ZipCPU|LaptopWell ... for a couple of reasons, but one of them was that the SD-Card controller I found on open cores only worked for SD mode, not SPI mode.17:46
olofkBut for your question, no, FuseSoC is designed to not put any requirements on cores17:46
olofkThere are some things you can do to better integrate with FuseSoC, but no formal requirements17:46
ZipCPU|LaptopIs there a public repository requirement?  OpenCores vs github?  Or ... is there a FuseSoC config file that should be included with the core?17:47
olofkFor example, if you use the vlog_tb_utils core in your testbench, you will automatically get command-line switches for breaking the simulation after a certain time, optional VCD generation, heartbeat monitor and things like that17:47
ZipCPU|LaptopWow ... that's a lot.  Is this documented anywhere?17:48
olofkZipCPU|Laptop: Not even that :) There are currently backends to handle cores from opencores, github, zip/tar.gz files or general git repos17:48
olofkAnd you don't have to put the .core file in your repo17:48
ZipCPU|LaptopBut ... wouldn't it make sense to place the .core file into the repo to facilitate FuseSoC integration?17:48
olofkMost cores have the .core file in the FuseSoC standard library, with just a section called [provider] to tell FuseSoC where to find it17:49
olofkZipCPU|Laptop: Yes and no. FuseSoC still needs to know where to find the cores, and I did it this way also so that I could add cores to the library without forcing the author to add a file17:49
olofkBecause frankly, it's hard form me to convice people to add some configuration file for their pet project17:50
ZipCPU|LaptopThat makes sense.17:50
olofkZipCPU|Laptop: Unfortunately there is extremely little documentation17:51
olofkBut if you run one of the better supported cores, like say, mor1kx-generic, you can run "fusesoc sim mor1kx-generic --help" to get a list of the switches for that system17:51
ZipCPU|LaptopOkay, well ... perhaps the code is self-documenting ;)  Is the FuseSoC code easily found?17:52
olofkEach core can register new command-line switches themselves. These are then translated to a top-level generic/parameter, a verilog plusargs or sent directly to the tool17:52
olofkThe code is here
olofkIt's not self-explaining, and I'm ashamed of the lack of documentation17:52
olofkI've tried to write some topic posts on my blog. You might find some clues there17:53
ZipCPU|LaptopI noticed a "doc" directory in your repo.  Is it worth much?17:53
olofkNot that much. Most of it consists of the available sections and options you can put in your .core file17:54
ZipCPU|LaptopAnd the orpsoc-cores directory contains examples of cores that use FuseSoC?17:55
olofkZipCPU|Laptop: Correct. I intend to rename it some day, but I usually refer to it as the "FuseSoC standard library"17:55
olofkIt's a remain from the early days of development when it was still called orpsocv317:56
olofkBefore I realized that there wasn't a single OpenRISC-specific line of code in the project :)17:56
olofkEven though many of the cores themselves still are OpenRISC-related17:56
ZipCPU|LaptopDoes it contain an SD card controller that works in SPI mode?  :?17:56
olofkI only added the one from OpenCores17:56
ZipCPU|LaptopI'll take that as a "no."17:57
olofkGoogle did a prototype of their ProjectVault that they showed at last year's Google I/O conference17:57
olofkTheir prototype used OpenRISC and was created with FuseSoC. I think that contains a SD card controller. You could check that out17:58
olofkOh... and I created .core files for the Pulpino project from ETH Zurich. There should be an SD card controller there I think17:58
olofkAhh. no. Sorry. That was a quad SPI one17:59
olofkOh.. but wait. stekern did a FuseSoC port of the minimig amiga emulator. That one most definitely uses an SPI controller to talk to the SD Cards17:59
olofkDoesn't look like he wrote any .core files for it though (or did you, stekern?), but that's quickly done18:01
ZipCPU|LaptopLooks like I've got some more research/work to do.  Thanks for the tips.18:01
olofkoh well. Time to sleep now. Happy to help out if you need any help. FuseSoC-related or not18:02
ZipCPU|Laptop(I've actually got the core written, just not working yet.  You know ... the first 5% of the work ;)  )18:02
shorneolofk: I'll look into signing, but I guess it pulls in a lot of fixes over the years (mainly peter's) I guess he must have signed.19:40
shorneAs per the patch to upstream, I think we need to separate out/remove the or1ksim lib stuff (we can use remote target anyway to run on or1ksim).  I guess since jeremybennett wrote the or1ksim target I would like to get his ok.19:43
shornewallento: I guess there might be a few more patches. We will need to squash actual upstream patch into a few large patches19:52
shorneolofk: FYI, some docs are here,  Not sure if my work so far is (significant)19:55
shorneIt looks liek the request for papers will be initialized once we submit to the gnu project maintainers (i.e. gdb maintainers)19:59
-!- Shentino2 is now known as Shentino22:43
--- Log closed Sun May 29 00:00:28 2016

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