IRC logs for #openrisc Tuesday, 2016-03-22

--- Log opened Tue Mar 22 00:00:46 2016
wallentoandrzejr: yep, I agree. do we have a proper AXI-WB bridge at hand? I remember I planned on starting one, but for some reason did not do it. wasn't there something in last years gsoc, olofk?03:20
olofkblueCmd did a wb axi bridge. I haven't packaged it for FuseSoC yet, and I IIRC it was only AXI4Lite03:36
olofkThe GSoC job from last year was wb to some weird internal lowRISC bus called TileLink03:37
olofkThe PULP guys slapped on a AXI4 IF to their OpenRISC core instead and dropped wb completely03:37
olofkAXI4 is arguably a better bus than wb, but I still have some reservations regarding the license03:38
olofkThe RISC-V guys decided to use another name for their AXI4 buses03:38
olofkIt would be nice to provide alternative bus interfaces for our most used cores03:39
olofkPlease note that a new bus interface is not the same as rewriting every single fucking core. I'm dead tired of people writing new SPI controllers and UARTs. We have like 500 of those damn things with slightly different address maps and where at least 495 of them lack a proper testbench, documentation and drivers03:42
olofkPulpino at least reused the i2c controller and adv_debug_sys that we're using and changed bus if and fixed some stuff03:43
olofkThey did a new SPI controller, but their seems to support Quad SPI so I guess that's fair enough03:45
olofkAny windows users who want to help out making FuseSoC run on windows?03:53
bandvigolofk: I used FuseSoC of very old version (at least 1.5 year ago) under CygWin64. Actually, I just generated tcl for Atlys with FuseSoC. Since time I use Xilinx GUI.04:04
bandvigIn my plan to play the freshest FuseSoC.04:05
andrzejrolofk, you mean this: ?04:21
andrzejrThe main problem with using AXI (trademark aside) is the bus master. At very least Mor1kx should support it and it is not trivial to add it (afair it currently assumes a bus with synchronous transactions). How is it done in pulpino?04:30
wallentoah, wait, there should be a wb2AXI bridge in lowrisc04:38
wallentolet me check04:38
andrzejrStupid me. Pulpino uses RISC-V.04:39
wallentoyou are just not allowed to call it AXI due to ARM licensing04:40
andrzejrIt looks like a nice implementation. I like it doesn't use custom HDLs (Chisel) or buses (TileLink). Not sure if their subset of system-verilog simulates in Icarus, though.04:41
wallentommh, no actually there is no wb2axi in lowrisc, wei used Xilinx IP for peripherals04:41
wallentoyeah, but their core (it's called RI5CY, pulpino is the SoC) lacks the features why tilelink is there04:42
wallentowhich is distributed cache coherency I think04:42
wallentoolofk: I am nearly done with the updated patch04:43
andrzejrDoesn't AXI4 have some support for that?04:43
wallentofor verilator04:43
wallentonope, not AXI04:43
wallentoits ACE or so04:43
wallentothe coherency interface04:44
wallentoyes, ACE04:44
andrzejrIMHO it would be better to add an out-of-band channel between CPUs than to come up with a completely new bus.04:45
wallentoIt is actually, the problem was more that there was only the out-of-band channel04:53
wallentoThere was no other bus than this one originally04:53
wallentothey used peripherals via CSRs04:53
wallentoolofk: I have pushed a (rebased) update for verilator05:23
wallentothe parameter name has changed to -pvalue+ instead of +parameter+05:23
wallentoone problem is that you cannot use strings in vc files05:26
olofkwallento: That shouldn't matter in my case. I'll pass the strings as command-line args06:52
wallentookay, great07:48
-!- Amadiro_ is now known as Amadiro08:43
-!- Netsplit *.net <-> *.split quits: _franck__13:32
andrzejrolofk, did you try simulating packaged pulpino cores in other simulators?17:35
--- Log closed Wed Mar 23 00:00:47 2016

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